<br />
CALL FOR PARTICIPATION<br />
<br />
2010 13th EUROMICRO Conference on Digital System Design<br />
"Architectures, Methods and Tools"<br />
DSD 2010, 1-3 September, Lille, France<br />
General Chairs: Henri Basson and Smail Niar<br />
Program Chair: Sebastian Lopez<br />
<br />
<br />
Full program, registration and other details available at:<br />
<a target="_blank"
href="http://www.iuma.ulpgc.es/dsd10/">http://www.iuma.ulpgc.es/dsd10/</a><br
/>
www.dsdconf.org<br />
<br />
<br />
KEYNOTES<br />
<br />
Keynote 1 - Wednesday 1st September<br />
Cyper-physical MPSoC System: Adaptive Multi-Core Architectures in the Nano
Era<br />
Jürgen Becker<br />
Karlsruhe Institute of Technology, Germany<br />
<br />
Keynote 2 - Thursday 2nd September<br />
Digital System Design for Remotely Sensed Hyperspectral Image Processing<br />
Antonio J. Plaza<br />
University of Extremadura, Spain<br />
<br />
Keynote 3 - Friday 3rd September<br />
Future Directions for Digital Systems Design - A Programmable Perspective<br />
Patrick Lysaght<br />
Xilinx Research Labs, San Jose, CA<br />
<br />
TECHNICAL SESSIONS<br />
<br />
WEDNESDAY 1st SEPTEMBER<br />
<br />
SCS-1: System and Circuit Synthesis (1)<br />
Optimization of Area and Delay at Gate-Level in Multiple Constant
Multiplications<br />
Aksoy, Levent (1); Costa, Eduardo (2); Flores, Paulo (1); Monteiro, José (1)<br
/>
1: INESC-ID, Lisbon, Portugal; 2: UCPEL, Pelotas-RS, Brazil<br />
Visualization of Multi-Objective Design Space Exploration for Embedded
Systems<br />
Taghavi Razavi Zadeh, Toktam; D. Pimentel, Andy<br />
University of Amsterdam, Netherlands, The<br />
Design of Trace-Based Split Array Caches for Embedded Applications<br />
Tokarnia, Alice M.; Tachibana, Marina<br />
School of Electrical and Computer Engineering/University of Campinas, Brazil<br
/>
Software Programmable Data Allocation in Multi-Bank Memory of SIMD Processors<br
/>
Wang, Jian; Sohl, Joar; Kraigher, Olof; Liu, Dake<br />
Linkoping University, Sweden<br />
<br />
S&N(oC)-1: Systems and Networks on Chip (1)<br />
A Novel Mechanism to Guarantee In-Order Packet Delivery with Adaptive Routing
Algorithms in Networks on Chip<br />
Palesi, Maurizio (1); Holsmark, Rickard (2); Wang, Xiaohang (3); Kumar, Shashi
(2); Yang, Mei (3); Jiang, Yingtao (3); Catania, Vincenzo (1) <br />
1: University of Catania, Italy; 2: Jonkoping University, Sweden; 3: University
of Nevada, USA<br />
Power Distribution in NoCs through a Fuzzy Based Selection Strategy for Adaptive
Routing<br />
Salehi, Nastaran (1); Khademzadeh, Ahmad (2); Dana, Arash (2) <br />
1: Islamic Azad University, Science and Research Branch, Tehran, Iran; 2: Iran
Telecommunication Research center, Tehran, Iran <br />
NoC switch with credit based guaranteed service support qualified for GALS
systems <br />
Kranich, Tim; Berekovic, Mladen<br />
TU Braunschweig, Germany<br />
A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-Chip
Networks <br />
Nguyen, Son Truong; Oyanagi, Shigeru<br />
Department of Computer Science, Ritsumeikan University, Japan<br />
<br />
RC-1: Reconfigurable Computing (1)<br />
Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration <br
/>
Shehan, Basher; Jahr, Ralf; Uhrig, Sascha; Ungerer, Theo <br />
University of Augsburg, Germany <br />
Creation of Partial FPGA Configurations at Run-Time <br />
Silva, Miguel (1); Ferreira, João Canas (1,2)<br />
1: FEUP, Portugal; 2: INESC Porto <br />
A Modular Peripheral to Support Self-Reconfiguration in SoCs <br />
Otero Marnotes, Andrés; Morales Cas, Ángel; Portilla, Jorge; De la Torre,
Eduardo; Riesgo, Teresa<br />
Universidad Politécnica de Madrid, Spain<br />
High level validation of an optimization algorithm for the implementation of
adaptive Wavelet Transforms in FPGAs <br />
Salvador, Rubén (1); Moreno, Félix (1); Riesgo, Teresa (1); Sekanina, Lukás
(2)<br />
1: Universidad Politécnica de Madrid, Spain; 2: Brno University of Technology,
Brno, Czech Republic <br />
<br />
SLEO: System Level Energy Optimization of HW/SW Embedded Systems<br />
Composable Dynamic Voltage and Frequency Scaling and Power Management for
Dataflow Applications <br />
Goossens, Kees (1); She, Dongrui (1); Molnos, Anca (2); Milutinovic, Aleksandar
(3) <br />
1: Eindhoven University of Technology, The Netherlands; 2: Delft University of
Technology, The Netherlands; 3: University of Twente, The Netherlands
<br />
A Markov Model for Low-Power High-Fidelity Design-Space Exploration<br />
Cao, Jing; Nymeyer, Albert <br />
University of New South Wales, Australia <br />
A Test Bench for Distortion-Energy Optimization of a DSP-Based H.264/SVC Decoder
<br />
Pescador del Oso, Fernando (1); Juarez Martinez, Eduardo (1); Samper Martinez,
David (1); Sanz Álvaro, César (1); Raulet, Mickaël (2) <br />
1: Universidad Politécnica de Madrid, Spain; 2: IETR/Image group Lab, Rennes,
France<br />
<br />
SCS-2: System and Circuit Synthesis (2)<br />
On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in
Asymmetric Channels<br />
Piestrak, Stanislaw J. <br />
IRISA/ENSSAT, France<br />
QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration<br
/>
Bode, Dennis; Berekovic, Mladen <br />
TU Braunschweig, Germany<br />
A C-to-RTL flow as an energy efficient alternative to embedded processors in
digital systems<br />
Desai, Madhav Pandurang; Sahasrabuddhe, Sameer D; Ghosh, Kunal P; Subramanian,
Sreenivas; Arya, Kavi<br />
Indian Institute of Technology Bombay, India<br />
Area and Speed Oriented Implementations of Asynchronous Logic Operating Under
Strong Constraints<br />
Fiser, Petr (1); Lemberski, Igor (2) <br />
1: Czech Technical University in Prague, Czech Republic; 2: Baltic International
Academy, Riga, Latvia<br />
<br />
S&N(oC)-2: Systems and Networks on Chip (2)<br />
A Latency-Efficient Router Architecture for CMP Systems<br />
Roca, Antoni; Flich, Jose; Silla, Federico; Duato, Jose <br />
Technical University of Valencia, Spain<br />
Trading hardware overhead for communication performance in mesh-type topologies
<br />
Cornelius, Claas; Kubisch, Stephan; Gorski, Philipp; Timmermann, Dirk <br
/>
University of Rostock, Germany <br />
Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms
<br />
Mubeen, Saad; Kumar, Shashi <br />
Jönköping University Sweden, Sweden<br />
<br />
MSDA-1: Multicore Systems: Design and Applications (1)<br />
Evaluating OpenMP support costs on MPSoCs <br />
Marongiu, Andrea; Burgio, Paolo; Benini, Luca <br />
University of Bologna, Italy<br />
Re-NUCA: Boosting CMP performance through block replication <br />
Solinas, Marco (1); Foglia, Pierfrancesco (1); Prete, Cosimo Antonio (1); Monni,
Giovanna (2) <br />
1: Università di Pisa, Italy; 2: IMT Institute for Advanced Studies <br
/>
Filtering Directory Lookups in CMPs <br />
Bosque, Ana (1); Viñals, Víctor (2); Ibáñez, Pablo (2); Llabería, Jose M. (1)
<br />
1: UPC, Spain; 2: Universidad de Zaragoza, Spain<br />
<br />
FTDSD-1: Fault Tolerance in Digital System Design (1)<br />
Low Latency Recovery from Transient Faults for Pipelined Processor
Architectures <br />
Jeitler, Marcus <br />
Vienna University of Technology, Austria <br />
RobuCheck: A Robustness Checker for Digital Circuits <br />
Frehse, Stefan; Fey, Goerschwin; Sueflow, Andre; Drechsler, Rolf <br />
University of Bremen, Germany<br />
Dynamic Control Flow Checking Technique for Reliable Microprocessors <br
/>
Sugihara, Makoto <br />
TUT, Japan<br />
<br />
Poster Session P-1<br />
Arithmetic units for RNS moduli $\{2^{n}-3\}$ and $\{2^{n}+3\}$ operations <br
/>
Matutino, Pedro Miguens (1); Chaves, Ricardo (2); Sousa, Leonel (2) <br
/>
1: ISEL / INESC-ID, Portugal; 2: IST / INESC-ID, Portugal<br />
Real-time Testing of True Random Number Generators through Dynamic
Reconfiguration <br />
Cret, Octavian Augustin; Hotoleanu, Dan; Suciu, Alin; Vacariu, Lucia <br
/>
Tehnical University of Cluj Napoca - Romania, Romania<br />
Instantiating GENESYS Application Architecture Modelling via UML 2.0 constructs
and MARTE Profile <br />
Khan, Subayal Aftab (1); Tiensyrjä, Kari (1); Nurmi, Jari (2) <br />
1: VTT Technical Research Centre of Finland; 2: Tampere University of
Technology<br />
An Improved Automotive Multiple Target Tracking System Design <br />
Lange, Tobias (1); Harb, Naim (2); Ben-Atitallah, Rabie (2); Liu, Haisheng (2);
Niar, Smail (2) <br />
1: Technical University of Braunschweig, Germany;<br />
2: University Of Lille North of France (ULNF), Valenciennes, France<br />
Medical Diagnosis Improvement through Image Quality Enhancement Based on
Super-Resolution <br />
G. Villanueva, Lara; M. Callicó, Gustavo; Tobajas, Félix; López, Sebastián; De
Armas, Valentín; López, José F.; Sarmiento, Roberto <br />
University of Las Palmas de Gran Canaria, Spain<br />
Generated Cycle-Accurate Profiler for C Language <br />
Prikryl, Zdenek; Masarik, Karel; Hruska, Tomas; Husar, Adam <br />
Brno University of Technology, Czech Republic<br />
Architecture Level Design Space Exploration of SuperScalar Microarchitecture for
Network Applications <br />
Salehi, Mostafa E; Dorosti, Hamed; Fakhraie, Sied Mehdi <br />
University of Tehran, Iran, Islamic Republic of<br />
<br />
SVMT-1: System, hardware and embedded-software specification, modeling,
verification and test (1)<br />
Simulation of High-Performance Memory Allocators <br />
Risco-Martín, José Luis; Colmenar, José Manuel; Atienza, David<br />
Universidad Complutense de Madrid, Spain<br />
Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel
Scan Structures <br />
Kothe, Rene <br />
BTU Cottbus, Germany <br />
Exploration of Network Alternatives for Middleware-centric Embedded System
Design <br />
Quaglia, Davide; Fummi, Franco; Perbellini, Giovanni; Trenti, Roberto<br />
University of Verona, Italy<br />
<br />
FDR: Flexible Digital Radio<br />
Adaptive Beamforming using the Reconfigurable Montium TP <br />
van de Burgwal, Marcel D.; Rovers, Kenneth C.; Blom, Koen C.H.; Kokkeler, André
B.J.; Smit, Gerard J.M.University of Twente, Netherlands, The<br />
A Common Operator for FFT and Viterbi algorithms <br />
Naoues, Malek; Alaus, Laurent; Noguet, Dominique <br />
CEA, France<br />
ALOE-based flexible LDPC decoder <br />
Gomez Miguelez, Ismael (1); Camatel, Massimo (1); Bracke, Jordi (1); Vacca,
Fabrizio (2); Marojevic, Vuk (1); Masera, Guido (2); Gelonch, Antoni<br />
1: Universitat Politecnica de Catalunya, Spain; 2: Dipartimento di Elettronica,
Politecnico di Torino, Italy<br />
Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA <br />
Recio, Adolfo; Athanas, Peter Virginia Tech, United States of America<br />
<br />
MSDA-2: Multicore Systems: Design and Applications (2)<br />
Adaptive Cache Memories for SMT Processors <br />
Lopez, Sonia (1); Garnica, Oscar (2); Albonesi, David H. (3); Dropsho, Steven
(4); Lanchares, Juan (2); Hidalgo, Ignacio (2) <br />
1: Rochester Institute of Technology, United States of America; 2: Universidad
Complutense de Madrid, SPAIN; 3: Cornell University, USA.; 4: Google, Inc
Zurich, Switzerland <br />
Multi-core Technology - Next Evolution Step in Safety Critical Systems for
Industrial Applications? <br />
Reichenbach, Frank; Wold, Alexander <br />
ABB, Norway<br />
A Case for Hardware Task Management Support for the StarSS Programming Model <br
/>
Meenderinck, Cor (1); Juurlink, Ben (2)<br />
1: Delft University of Technology, Netherlands, The; 2: Technische Universitat
Berlin, Germany<br />
On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable
Platforms <br />
Kornaros, George; Motakis, Antonis <br />
Technological Educational Institute of Crete, Dept. of Applied Informatics &
Multimedia, Greece<br />
<br />
FTDSD-2: Fault Tolerance in Digital System Design (2)<br />
Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic Reconfiguration
<br />
Straka, Martin; Kastil, Jan; Kotasek, Zdenek <br />
Brno University of Technology, Czech Republic<br />
System Level Hardening by Computing with Matrices <br />
Ferreira, Ronaldo Rodrigues; Moreira, Álvaro Freitas; Carro, Luigi <br />
Instituto de Informática, Universidade Federal do Rio Grande do Sul, Brazil
<br />
Faults Coverage Improvement based on Fault Simulation and Partial Duplication
<br />
Borecký, Jaroslav; Kohlík, Martin; Kubátová, Hana; Kubalík, Pavel <br />
Czech Technical University in Prague, Czech Republic<br />
<br />
<br />
THURSDAY 2nd SEPTEMBER<br />
<br />
<br />
Poster Session P-2<br />
A Class of Recursive Networks on a Chip for Enhancing Intercluster Parallelism
<br />
Takesue, Masaru <br />
Hosei University, Japan<br />
A programming model and a NoC-based architecture for streaming applications
<br />
Houzet, Dominique; Huet, Sylvain; Wu, Yun-Jie <br />
Grenoble INP, France<br />
Scalable Architecture for Wavelength-Switched Optical NoC With Multicasting
Capability <br />
Koohi, Somayyeh; Shafaei, Alireza; Hessabi, Shaahin <br />
Sharif University of Technology, Iran, Islamic Republic of<br />
Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application
<br />
Kumar, Pankaj; Kumar, Deepak; Pattanaik, Manisha<br />
ABV-Indian Institute of Information Technology and Management, Gwalior, India<br
/>
Area-Efficient Multi-Moduli Squarers for RNS<br />
Bakalis, Dimitris; Vergos, Haridimos T. <br />
University of Patras, Greece<br />
A Load-Forwarding Mechanism for the Vector Architecture in Multimedia
Applications <br />
Gao, Ye (1); Egawa, Ryusuke (2,3); Takizawa, Hiroyuki (1,3); Kobayashi, Hiroaki
(2,3) <br />
1: Graduate School of Information Sciences, Tohoku University; 2: Cyberscience
Center, Tohoku University; 3: JST CREST<br />
Low Power FPGA Implementations of 256-bit Luffa Hash Function<br />
Kitsos, Paris (1); Sklavos, Nicolas (2); Skodras, Athanassios (3) <br />
1: Hellenic Open University, Greece; 2: Technological Educational Institute of
Patras, Greece; 3: Hellenic Open University, Greece<br />
On the Numbers of Variables to Represent Multi-Valued Incompletely Specified
Functions<br />
Sasao, Tsutomu <br />
Kyushu Ins. of Tech, Japan<br />
<br />
SCS-3: System and Circuit Synthesis (3)<br />
Unified Digit Serial Systolic Montgomery Multiplication Architecture for Special
Classes of Polynomials over GF(2^m)<br />
Rahaman, Hafizur; Talapatra, Somsubhra <br />
Bengal Engineering and Science University, Shibpur, India<br />
An Improved Hardware Implementation of the Grain Stream Cipher<br />
Sharif Mansouri, Shohreh; Dubrova, Elena <br />
KTH, Sweden<br />
Description-level Optimisation of Synthesisable Asynchronous Circuits<br />
Tarazona Duarte, Luis Antonio; Edwards, Douglas; Bardsley, Andrew Plana, Luis
<br />
The University of Manchester, United Kingdom<br />
A parallel for loop memory template for a high level synthesis compiler<br />
Moore, Craig; Stroobandt, Dirk; Meeus, Wim; Devos, Harald <br />
Ghent University, Belgium <br />
<br />
S&N(oC)-3: Systems and Networks on Chip (3)<br />
In-Channel Flow Control Scheme for Network-on-Chip <br />
Nimbalkar, Vrishali Vijay (1); Varghese, Kuruvilla (2)<br />
1: Finolex Academy of Management and Technology, India; 2: Center for Electronic
Design and Technology, IISc Bangalore, India <br />
An Efficient Method to Reliable Data Transmission in Network-on-Chips<br />
Patooghy, Ahmad; Tabkhi, Hamed; Miremadi, Seyed Ghassem <br />
Sharif University of Technology, Iran, Islamic Republic of <br />
Network-on-Multi-Chip (NoMC) for multi-FPGA multimedia systems <br />
Stepniewska, Marta; Luczak, Adam; Siast, Jakub <br />
Poznan University of Technology, Poland <br />
Persistence Management Model for Dynamically Reconfigurable Hardware <br />
Dondo, Julio Daniel; Rincon, Fernando; Barba, Jesus; Moya, Francisco; Sanchez,
Francisco; Lopez, Juan Carlos<br />
Universidad de Castilla-La Mancha, Spain<br />
<br />
WSN: Wireless Sensor Networks<br />
System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes <br />
Pasha, Muhammad Adeel; Derrien, Steven; Sentieys, Olivier <br />
IRISA-INRIA, University of Rennes1, France<br />
A Traffic Differentiation Add-On to the IEEE 802.15.4 Protocol <br />
Severino, Ricardo; Batsa, Manish; Alves, Mário; Koubaa, Anis<br />
CISTER-ISEP, Portugal <br />
Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI
Environments <br />
Lavratti, Felipe (1); Pinto, Alex (2); Bolzani Pöhls, Leticia Maria (1); Vargas,
Fabian (1); Montez, Carlos (2); Hernandez, Fernando (3); Gatti, Edmundo (4);
Silva, Carlos (5)<br />
1: Catholic University of Rio Grande do Sul - PUCRS, Brazil; 2: Universidade
Federal de Santa Catarina - UFSC, Brazil; 3: Unidad Reguladora de Servicios de
Comunicaciones - URSEC, Uruguay; 4: Instituto Nacional de Tecnologia Industrial
- INTI, Argentina; 5: Pontificia Universidad Católica del Peru, Peru<br />
<br />
DTDS-1: Dependability and Testing of Digital Systems (1)<br />
Path-Delay Fault testing in Embedded Content Addressable Memories <br />
Palanichamy, Manikandan; Larsen, Bjørn; Aas, Einar <br />
The Norwegian University of Science and Technology (NTNU), Norway<br />
Application Dependent FPGA Testing Method Using Compressed Deterministic Test
Vectors <br />
Rozkovec, Martin; Novák, Ondrej; Jenicek, Jiri<br />
Technical University in Liberec, Czech Republic<br />
On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a
NoC as a Test Access Mechanism <br />
Zhang, Xiao (1); Kerkhoff, Hans G. (1); Vermeulen, Bart (2)<br />
1: CTIT, University of Twente, the Netherlands;<br />
2: Distributed Systems Architectures Group, NXP Semiconductors, the Netherlands
<br />
<br />
SCS-4: System and Circuit Synthesis (4)<br />
Behavioural modelling of DLLs for fast simulation and optimisation of jitter and
power consumption<br />
Barajas, Enrique; Mateo, Diego; González, José Luis<br />
Universitat Politecnica Catalunya, Spain<br />
A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic
Behaviour<br />
Stuijk, Sander (1); Geilen, Marc (1); Basten, Twan (1,2) <br />
1: Eindhoven University of Technology, The Netherlands; 2: Embedded Systems
Institute, The Netherlands<br />
A design process for harware/software system co-design and its application to
designing a reconfigurable FPGA<br />
Moreno, Felix; Lopez, Ignacio; Sanz, Ricardo <br />
Universidad Politécnica de Madrid (ETSII-UPM), Spain<br />
Optimising Self-timed FPGA circuits<br />
Ferguson, Phillip David (1); Efthymiou, Aristides (2); Arslan, Tughrul (2);
Hume, Danny (3)<br />
1: Institute Of System Level Integration, United Kingdom; 2: University Of
Edinburgh, United Kingdom; 3: Thales Optronics Ltd, Glasgow, United Kingdom<br
/>
<br />
S&N(oC)-4: Systems and Networks on Chip (4)<br />
A new high-level methodology for programming FPGA-based smart camera <br />
Roudel, Nicolas (1); Berry, François (1); Sérot, Jocelyn (1); Eck, Laurent
(2)<br />
1: LASMEA UMR6602, France; 2: CEA, LIST, France<br />
Power consumption modeling for DVFS exploitation <br />
Andrea, Castagnetti; Cécile, Belleudy; Sébastien, Bilavarn; Michel, Auguin<br />
LEAT Université de Nice - CNRS, France <br />
Automated Power Characterization for Run-Time Power Emulation of SoC Designs <br
/>
Bachmann, Christian <br />
Graz University of Technology, Austria<br />
Customizable Composition and Parameterization of Design Transformations
<br />
Todman, Timothy John; Liu, Qiang; Luk, Wayne; Constantinides, George A<br />
Imperial College London, United Kingdom <br />
<br />
ET: Emerging technologies<br />
Architectural Vulnerability Factor Estimation with Backwards Analysis <br />
Hartl, Robert (1); Rohatschek, Andreas J. (1); Stechele, Walter (2);
Herkersdorf, Andreas (2)<br />
1: Robert Bosch GmbH, Germany; 2: Institute for Integrated Systems, Technische
Universität München, Germany <br />
Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA
Logic Circuit <br />
Sen, Bibhash (1); Sengupta, Anik (2); Dalui, Mamta (3); Sikdar, Biplab K (4)<br
/>
National Institute o Technology Durgapur, India; 2: National Institute o
Technology Durgapur, India; 3: Bengal Engineering and Science University,
Shibpur; 4: Bengal Engineering and Science University, Shibpur<br />
Evaluation of RTD-CMOS Logic Gates <br />
Nunez, Juan; Avedillo, Maria J.; Quintana, Jose M.<br />
IMSE-CNM-CSIC, Spain <br />
On CMOS Memory Design In Low Supply Voltage For Integrated Biosensor
Applications<br />
Chen, Tom <br />
Colorado State University, United States of America<br />
<br />
DTDS-2: Dependability and Testing of Digital Systems (2)<br />
A Formal Condition to Stop an Incremental Automatic Functional Diagnosis <br />
Amati, Luca (1); Bolchini, Cristiana (1); Salice, Fabio (1); Franzoso, Federico
(2)<br />
1: Politecnico di Milano, Italy; 2: Cisco Photonics<br />
The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan
Register Sequences and Reduce Power Consumption <br />
Kotasek, Zdenek; Skarvada, Jaroslav; Strnadel, Josef<br />
Brno U. of Tech, Czech Republic <br />
Multiple Bit Error Detection and Correction in Memory <br />
Argyrides, Costas (3); Tarrillo, Jimmy (2); Lisboa, Carlos (2); Pradhan, Dhiraj
(1); Carro, Luigi (2)<br />
1: University of Bristol, United Kingdom; 2: Instituto de Informática, PPGC
Universidade Federal do Rio Grande do Sul; 3: C. A. evolvIT LTD, Limassol,
Cyprus<br />
<br />
<br />
FRIDAY 3rd SEPTEMBER<br />
<br />
<br />
SCS-5: System and Circuit Synthesis (5)<br />
Design methodology for a high performance robust DVB-S2 decoder
implementation<br />
Berthelot, Florent; Charot, François; Wagner, Charles; Wolinski, Christophe<br
/>
Inria Rennes Irisa, France<br />
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor <br />
Waqar, Muhammad; Thanh Hoang, Tung; Larson-Edefors, Per<br />
Chalmers University of Technology, Sweden<br />
A Memetic Approach for CMOL Cell Mapping <br />
Zhufei, Chu (1); Yinshui, Xia (1); William, N.N. Hung (2); Xiaoyu, Song (3);
Lunyao, Wang (1)<br />
1: Ningbo University, China, Peoples Republic of; 2: Synopsys, Inc., USA; 3:
Portland State University, USA<br />
Static Average Case Power Estimation Technique for Block Ciphers <br />
Chen, Jiaoyan; Ye, Tingcong; Vasudevan, Dilip; Popovici, Emanuel; Schellekens,
Michel<br />
University College Cork, Ireland, Republic of<br />
<br />
SVMT-2: System, hardware and embedded-software specification, modeling,
verification and test (2)<br />
An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits <br
/>
Rutgers, Jochem H. (1); Wolkotte, Pascal T. (2); Hölzenspies, Philip K.F. (1);
Kuper, Jan (1); Smit, Gerard J.M. (1)<br />
1: University of Twente, Netherlands, The; 2: Alcatel-Lucent, Belgium<br />
Modeling reconfigurable Systems-on-Chips with UML MARTE profile: an exploratory
analysis <br />
Cherif, Sana; Quadri, Imran; Meftali, Samy; Dekeyser, Jean-Luc <br />
INRIA Lille-Nord Europe / LIFL / USTL / CNRS, France<br />
C?aSH: Structural Descriptions of Synchronous Hardware using Haskell <br />
Baaij, Christiaan; Kooijman, Matthijs; Kuper, Jan; Boeijink, Arjan; Gerards,
Marco <br />
University of Twente, Netherlands, The<br />
Storage-Aware Value Prediction <br />
Baniasadi, Amirali (1); Salehi, Mohammad (2)<br />
1: University of Victoria, Canada; 2: Sharif University of Technology<br />
<br />
APP: Applications of (embedded) digital systems<br />
Computation Reduction Techniques for Vector Median Filtering and their Hardware
Implementation <br />
Tasdizen, Ozgur; Hamzaoglu, Ilker<br />
Sabanci University, Turkey<br />
A Novel VLSI Architecture of Fixed-complexity Sphere Decoder <br />
Wu, Bin; Masera, Guido<br />
Politecnico di Torino, Italy<br />
A Packet Classifier Using a Parallel Branching Program Machine <br />
Nakahara, Hiroki; Sasao, Tsutomu; Matsuura, Munehiro <br />
Kyushu Institute of Technology, Japan<br />
A Computation and Power Reduction Technique for H.264 Intra Prediction <br />
Adibelli, Yusuf; Parlak, Mustafa; Hamzaoglu, Ilker <br />
Sabanci University, Turkey<br />
<br />
RC-2: Reconfigurable Computing (2)<br />
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance <br />
Sajid, Imtiaz (1); Ziavras, Sotirios (1); Ahmed, M (2)<br />
1: New Jersey Institute of Technology, United States of America; 2: Mohammad Ali
Jinnah University, Islamabad, Pakistan<br />
An FPGA-based Accelerator for Analog VLSI Artificial Neural Network Emulation
<br />
van Liempd, Barend (1); Herrera Peña, Daniel (2); Figueroa Toro, Miguel (2)<br
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1: Eindhoven University of Technology, Netherlands, The; 2: University of
Concepción, Chile<br />
A Multicore Embedded Processor For Fingerprint Recognition <br />
Leporati, Francesco; Danese, Giovanni; Giachero, Mauro; Nazzicari, Nelson
<br />
University of Pavia, Italy<br />
H.264 Color Components Video Decoding Parallelization on Multi-Core Processors
<br />
Baaklini, Elias (1); Sbeity, Hassan (1); Niar, Smail (2)<br />
1: Arab Open University, Beirut, Lebanon; 2: University Of Lille North of France
(ULNF), Valenciennes, France<br />
<br />
Poster Session P-3<br />
New Digital Control Technique for Improving Transient Response in DC-DC
Converters Batarseh, Majd Ghazi; Shobaki, Ehab; Fang, Xiang; Hu, Haibing;
Batarseh, Issa<br />
University of Central Florida, United States of America<br />
A Fast Analytical Approach to Multi-Cycle Soft Error Rate Estimation of
Sequential Circuits<br />
Fazeli, Mahdi; Miremadi, Seyed Ghassem; Asadi, Hossein; Baradaran Tahoori,
Mehdi<br />
Sharif Uni. of Technology, Iran, Islamic Republic of<br />
A Multicore SDR Architecture for Reconfigurable WiMAX Downlink <br />
Suárez Casal, Pedro; Carro Lagoa, Ángel; García Naya, José Antonio; Castedo
Ribas, Luis<br />
Universidade da Coruña, Spain<br />
Test Patterns Compression Technique Based on a Dedicated SAT-based ATPG
Balcarek, Jiri (1); Fiser, Petr (2); Schmidt, Jan (2)<br />
1: Czech Technical University in Prague, FEL; 2: Czech Technical University in
Prague, FIT<br />
Gracefully Degrading Circuit Controllers Based on Polytronics <br />
Ruzicka, Richard <br />
Brno University of Technology, Czech Republic<br />
LEON3 ViP : a Virtual Platform with Fault Injection capabilities <br />
Da Silva, Antonio (1); Sánchez Prieto, Sebastián (2); Martínez Ortega, José
Fernán (1); García Hernando, Ana Belen (1); López Santidrian, Lourdes (1);
Hernández Díaz, Vicente (1)<br />
1: Technical University of Madrid, Spain; 2: University of Alcalá, Spain<br />
Reconfigurable Fault-Tolerant System Sychronization <br />
Balach, Jan; Novak, Ondrej<br />
CTU in Prague, Czech Republic<br />
Structurally Synthesized Multiple Input BDDs for Speeding up Logic-Level
Simulation of Digital Circuits <br />
Mironov, Dmitri; Ubar, Raimund; Devadze, Sergei; Raik, Jaan; Jutman, Artur<br />
Tallinn Tech. U, Estonia <br />
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