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</o:shapelayout></xml><![endif]--></head><body lang=EL link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span lang=EN-US>===============================================================<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>DSD'2011 CALL FOR PAPERS<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>14th EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Architectures, Methods and Tools<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Oulu, Finland, August 31 – September 2, 2011<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>http://dsmc2.eap.gr/dsd2011/<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>===============================================================<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>[IMPORTANT DATES]<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>- Submission of papers: March 14, 2011<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>- Notification of acceptance: April 24, 2011<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>- Camera ready papers: May 29, 2011<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>[SCOPE]<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed hardware/software system engineering, down to microarchitectures, digital circuits and VLSI techniques. It is a discussion forum for researchers and engineers from academia and industry working on state-of-the-art investigations, development and applications. It focuses on advanced circuit and system design and design automation concepts, paradigms, methods and tools, as well as on modern implementation technologies from full custom in nanometer technology nodes to FPGA and to multicore infrastructures. Compiler assisted ASIP, CMP, SMP, SMT, DSP-VLIW, GPU and platform based system design research results are welcome. Design and Verification Languages and Standards, High Level Synthesis, Efficiency, Density, Signal Integrity, Testability, Timing Analysis and Timing Closure, Asynchronous Techniques, Reconfigurable Architectures, Power Consumption, Computational Power Speed and Performance, Productive Design Technology and Engineering Flows, Manufacturability, Cost, Reliability, Error Resilience, Complexity, or Process Variability issues, Modeling, Design Experiences are covered in DSD. <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>The IEEE Conference Publishing Services (CPS), publishes the DSD Proceedings, which are available worldwide through the IEEE Xplore Digital Library. An extended version of the best papers will be published in a special issue of the ISI-indexed Microprocessors and Microsystems: Embedded Hardware Design journal, printed by Elsevier.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>[MAIN TOPICS]<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>T1: (SHES) - System, hardware and embedded software design and automatic synthesis: high-level, behavioral, register-transfer, logic and physical circuit synthesis; arithmetic, signal processing and vector processing units; graphics processing units and hardware accelerators; memory design; communication architecture and protocols; specific circuits and processors; multi-objective optimization observing power, performance, communication traffic, interconnect architecture, layout, technology, reliability, robustness, security, testability and other issues; management of parallel computational resources, memory allocation and hierarchy; hardware/software co-design; mapping of applications to architectures; algorithm architecture matching; transaction level modeling and higher-level modeling; virtual system prototyping; design space exploration; synthesis of asynchronous and dataflow driven systems, nanoelectronics; CAD for placement, routing, retiming, logic optimization, technology mapping, system-level partitioning, logic generators, testing and verification; CAD for modeling, analysis and optimization of timing and power.. <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>T2: (SoC & NoC) - Systems-on-a-chip and networks-on-a-chip: multiprocessor systems on-a-chip (MPSoC), generic system platforms and platform-based design; CMP, SMP, SMT, DSP, VLIW and ASIP (multi)processor architectures and enhancements; 3D MPSoCs; software design and programming models for multicore platforms; benchmarks; GPUs; cell-based platforms; NoC architectural issues, quality of service in NoCs; 3D NoCs; power dissipation and energy issues in SoCs and NoCs; IP design, standardization and reuse; parallelism and scalability techniques; virtual components; system on a system; compiler assisted MPSoC; hardware support for embedded kernels; embedded software features; static, run-time and dynamic optimizations of embedded systems. <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>T3: (RC) - Programmable/re-configurable/adaptable architectures: design methodologies and tools for reconfigurable computing, run-time, partial and dynamic reconfigurability; fine-grained, mixed-grained and coarse-grained reconfigurable architectures; reconfigurable interconnections and NoCs; FPGAs; systems on re-configurable chip; system FPGAs and structured ASICs and co-processors; processing arrays; programmable fabrics; novel logic block architectures, combination of FPGA fabric and system blocks (DSP, processors, memories, etc.); adaptive computing devices, systems and software; adaptable ASIPs and ASIP-based SOCs, hardware accelerators; optimization of FPGA-based cores; shared resource management; novel design algorithms for FPGA features; high-level models and tools for FPGAs; rapid prototyping systems and platforms; wireless and mobile systems. <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>T4: (SMVT) - System, hardware and embedded-software specification, modeling, verification and test: design, modeling, simulation and verification languages; functional, structural and parametric specification and modeling, model-based design and verification; system, hardware, and embedded software analysis; simulation, emulation, prototyping, formal verification, design-for-test and testing at all design levels; dependability and fault-tolerance issues. <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>T5: (APP) - Applications of (embedded) digital systems: emphasis on design challenges posed by demanding and new applications in fields such as: (wireless) communication and networking; networked electronic media, multimedia and ambient intelligence; image and video processing; mobile systems; health-care and medicine; ubiquitous, wearable and implanted systems; military, space, avionics, measurement, control and automotive applications; wireless sensor network applications; surveillance and security; environmental, agriculture, urban, building, transportation, traffic, energy, hazards and disasters monitoring and control. <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>T6: (ET) - Important issues introduced by emerging technologies: issues for the system, circuit and embedded software design introduced by e.g. the nanometer CMOS and beyond CMOS technologies, 3D integration, optical and new memory technologies etc.; new human-machine interfaces, neural- and bio-computation, (bio)sensor and sensor network technologies, pervasive and ubiquitous computing, 'internet of things'; design methods and EDA tools for solving these issues. <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>[SPECIAL SESSIONS]<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>Special sessions already accepted, and now accepting paper submissions: <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>? SS1: (FDR) - Flexible Digital Radio.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>? SS2: (MSDA) - Multicore Systems: Design and Applications.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>? SS3: (DTDS) - Dependability and Testing of Digital Systems.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>? SS4: (FTDSD) - Fault Tolerance in Digital System Design.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>? SS5: (SLEO) - System-Level Energy Optimization of HW/SW Embedded Systems.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>? SS6: (WSN) - Wireless Sensor Networks.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>? SS7: (AHSA) - Architectures and Hardware for Security Applications.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>More information on special sessions: http://dsmc2.eap.gr/dsd2011/index.php?page=8 <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>[SUBMISSION GUIDELINES]<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>Regular Papers: Prospective authors are encouraged to submit their manuscripts for review electronically through the following web page (https://www.conftool.net/dsd2011/) or by sending the paper to the Program Chair via email (pkitsos@eap.gr, only if an unexpected web access problem is encountered) before the deadline for submission. Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the required IEEE format: single-spaced, double column, A4/US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors' names should appear in the submitted manuscript, references included.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>Case Studies and Application Papers: Submissions can be made which report on state-of-the-art digital systems, digital designs, architectures, design methods and/or tools, and (embedded) applications. Papers discussing lessons learned from practical experience, demanding or new applications, and experimental research are particularly encouraged. Manuscripts may be submitted in the same way as regular papers.<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US> <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>[CONFERENCE COMMITTEES]<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>DSD STEERING COMMITTEE:<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Chairman: Lech Jozwiak, Eindhoven U. of Tech. (NL)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Krzysztof Kuchcinski, Lund U. (SE)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Antonio Nunez, IUMA/U. Las Palmas GC (ES)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>DSD11 GENERAL CHAIR:<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Pekka Abrahamsson, University of Helsinki, (FI)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>DSD11 PROGRAM COMMITTEE CHAIR:<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Program Chairman: Paris Kitsos, Hellenic Open Univ., (GR)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Deputy Program Chairman: Smail Niar, U. Lille North France, Valencienne, (FR)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>DSD11 LOCAL ORGANIZING CHAIR:<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Chair: Pasi Kuvaja, University of Oulu, (FI)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>DSD11 PROGRAM COMMITTEE:<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>A. Akkas, St. Cloud State U., (US)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>A. Lastovetsky, University College Dublin, (IR) <o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>A. Nunez, IUMA/U. of Las Palmas G.C., (ES)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>A. Orailoglu, U. of California, San Diego, (US)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>A. Pawlak, ITE & SUT, (PL)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>A. Postula, U. of Queensland, (AU)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>A. Shrivastava, Arizona State U., (US)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>B. Juurlink, TU Berlin (DE)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>C. Bouganis, Imperial College, (UK)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>C. Cornelius, U. of Rostock, (DE)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>C. Wolinski, IRISA, Rennes, (FR)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>D. Houzet, Grenoble Institute of Technology, (FR)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>D. Noguet, Minatec CEA-LETI, (FR)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>D. Quaglia, U. of Verona, (IT)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>E. Martins, U. of Aveiro, (PT)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>F. Leporati, U. of Pavia, (IT)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>G. Danese, U. Of Pavia, (IT)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>H. Basson, U. of Littoral, (FR)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>H. Kubatova, CTU Prague, (CZ)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>H.T. Vierhaus, Brandenburg U. of Tech., (DE)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>I. Hamzaoglu, Sabanci U., (TK)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>J. Haid, Infineon Technologies, (AT)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>J. Rabaey, U. of California, Berkeley, (US)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>J. Sahuquillo, Pol. U. of Valencia, (ES)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>J. Tiberghien, U. Libre de Bruxelles, (BE)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>J.L. Dekeyser, U. of Lille, (FR)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>J.S. Matos, U. of Porto, (PT)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>K. Kent, U. of New Brunswick, (CA)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>K. Kuchcinski, Lund U., (SE)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>K. Popovici, Mathworks Inc., (US)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>L. Benini, U. of Bologna, (IT)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>L. Fanucci, U. of Pisa, (IT)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>L. Jozwiak, Eindh. U. of Tech., (NL)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>L. Sousa, U. of Lisboa, (PT)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>L.-G. Chen, National Taiwan U., (TW)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>M. Berekovic, TU Braunschweig (DE)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>M. Figueroa, U. of Concepcion, (CL)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>M. K. Michail, U. of Cyprus, (CY)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>M. Perkowski, Portland St. U., (US)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>M. Valero, Pol. U. of Catalunya, (ES)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>M. Velev, Aries Design Automation, (US)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>N. Dutt, U. of Calif., Irvine, (US)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>N. Nedjah, State U. of Rio de Janeiro, (BR)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>N. Sklavos, Tech. Inst. Patras, (GR)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>O. Koufopavlou, U. Patras, (GR)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>P. Carballo, IUMA/U. of Las Palmas GC, (ES)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>P. Kitsos, Hellenic Open U., (GR)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>P. Schumacher, Xilinx Inc., (US)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>R. Drechsler, U. of Bremen, (DE)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>R. Cumplido, INAOE, (MX)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>R. Ubar, Tallinn Tech. U., (EE)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>S. Kumar, Jonkoping U., (SE)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>S. Lopez, IUMA/U. of Las Palmas G.C., (ES)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>S. Niar, U. Valenciennes, (FR)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>S. Vitabile, U. of Palermo, (IT)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>T. El-Ghazawi, George Washington U., (US)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>T. Luba, Warsaw U. of Tech., (PL)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>T. Sasao, Kyushu Ins. of Tech., (JP)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>V. Muthukumar, U. of Nevada Las Vegas, (US)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>V. Prasanna, U. of Southern California, (US)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>W. Luk, Imperial College, (UK)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>W. Stechele, Technical U. Munich, (DE)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Z. Kotasek, Brno U. of Tech., (CZ)<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US><o:p> </o:p></span></p><p class=MsoNormal><span lang=EN-US>DSD permanent homepage is at:<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>http://www.ics.ele.tue.nl/~dsd/<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>US mirror:<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>http://www.dsdconf.org/<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>Euromicro homepage is at:<o:p></o:p></span></p><p class=MsoNormal><span lang=EN-US>http://www.euromicro.org/<o:p></o:p></span></p><p class=MsoNormal>===============================================================<o:p></o:p></p></div></body></html>