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<P style="MARGIN: 0cm 0cm 0pt" class=MsoNormal><FONT size=3><FONT size=2 face="Courier New"><STRONG> *** CALL FOR PAPERS ***<BR> 26th IEEE International SoC Conference (SOCC2013)<BR> September 04 – 06, 2013</STRONG></FONT></FONT></P>
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<P style="MARGIN: 0cm 0cm 0pt" class=MsoNormal><FONT size=3><FONT size=2 face="Courier New"><STRONG> Fraunhofer Institute for Integrated Circuits (IIS)<BR> Erlangen (near Nuremberg), Germany</STRONG></FONT></FONT></P>
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<P style="MARGIN: 0cm 0cm 0pt" class=MsoNormal><FONT size=3><FONT size=2 face="Courier New">The SOC Conference is a premier forum for sharing advances in SoC technologies <BR>and applications in the areas of digital systems, circuit architectures, design <BR>methods, tools, automation, manufacturing, test, and emerging technologies. <BR>The 26th SOCC will be held at Fraunhofer IIS in Erlangen, Germany and will offer <BR>three days of technical papers, technical workshops, a vendor exhibition and <BR>an “IIS-lab-tour”. For updates and travel advice please check our website <BR>regularly <A href="http://www.ieee-socc.org">http://www.ieee-socc.org</A> or follow us on twitter <A href="mailto:“@ieee_socc">“@ieee_socc</A>” <BR>(or <A href="http://twitter.com/ieee_socc">http://twitter.com/ieee_socc</A>). contact: <A href="mailto:info@ieee-socc.org">info@ieee-socc.org</A></FONT></FONT></P>
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<P style="MARGIN: 0cm 0cm 0pt" class=MsoNormal><FONT size=3><FONT size=2 face="Courier New"><STRONG>SUBMISSION OF PAPERS AND WORKSHOP/TUTORIAL PROPOSALS</STRONG><BR> Electronic paper submissions are in pdf format, limited to six double-column <BR> IEEE format pages. The SOCC proceedings will be published on IEEE Xplore®. <BR> Embedded tutorial proposals with title, a half-page summary, and speaker's <BR> short bio are submitted to the Tutorial Chair.</FONT></FONT></P>
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<P style="MARGIN: 0cm 0cm 0pt" class=MsoNormal><FONT size=3><FONT size=2 face="Courier New"><STRONG>SOCC TECHNICAL SCOPE</STRONG><BR>Papers are invited which address new and previously unpublished results in </FONT></FONT></P>
<P style="MARGIN: 0cm 0cm 0pt" class=MsoNormal><FONT size=3><FONT size=2 face="Courier New">the areas:<BR> • Analog and Mixed-Signal Circuits and Systems<BR> • Biomedical Circuits and Systems<BR> • Wireline and Wireless Communication Circuits and Systems<BR> • Digital Signal Processing (DSP) Circuits and Systems<BR> • Green Circuits, Systems, and Design Methodologies<BR> • Embedded Systems, Multi/Many Core Systems and Embedded Memory Technologies<BR> • Network on Chip (NoC), Interconnects, and 3D-IC<BR> • Reconfigurable and Programmable Circuits and Systems<BR> • System Level Design Methodology and tools<BR> • Design for Testability and Manufacturability<BR> • Design Verification</FONT></FONT></P>
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<P style="MARGIN: 0cm 0cm 0pt" class=MsoNormal><FONT size=3><FONT size=2 face="Courier New"><STRONG>IMPORTANT DATES</STRONG><BR> Abstract and tutorial proposal submission deadline: April 8th, 2013<BR> Paper submission deadline: April 15th, 2013<BR> Notification of acceptance: June 10th, 2013<BR> Final camera-ready paper due: June 24th, 2013</FONT></FONT></P>
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<P style="MARGIN: 0cm 0cm 0pt" class=MsoNormal><FONT size=3><FONT size=2 face="Courier New"><STRONG>ORGANIZING COMMITTEE</STRONG><BR> Conference General Chair: Norbert Schuhmann, Fraunhofer IIS<BR> Technical Program Chair: Kaijian Shi, Cadence Design Systems<BR> Technical Program Co-Chair: Nagi Naganathan, LSI Corp<BR> Tutorial Chair: YuejianWu, Infinera<BR> Steering Committee Chair: Ramalingam Sridhar, SUNY at Buffalo<BR> Europe Liaison: Sakir Sezer, Queen’s Univ. Bellfast<BR> Asia Liaison: Sao-Jie Chen, National Taiwan University<BR> Industry Liaison: Andrew Marshall</FONT></FONT></P>
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