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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-family:"@Arial Unicode MS","sans-serif"'>[Apologies if you receive multiple copies of this CFP.] </span><span style='color:#1F497D'><o:p></o:p></span></p><pre style='text-align:center'><span lang=SV>============================================================================================<o:p></o:p></span></pre><pre style='text-align:center'><span lang=SV>CALL FOR PAPERS<o:p></o:p></span></pre><pre style='text-align:center'><b>On-chip Communication Architectures for Multi-Core and Many-Core Systems (OCA-MC)<o:p></o:p></b></pre><pre style='text-align:center'><span style='color:windowtext'>Special session in IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-15)<o:p></o:p></span></pre><pre style='text-align:center'><span style='color:#1F497D'><a href="http://mcsoc-forum.org/2015/?page_id=14">http://mcsoc-forum.org/2015/?page_id=14</a><o:p></o:p></span></pre><pre style='text-align:center'><span lang=SV style='color:windowtext'>23-25 September 2015, Turin, Italy<o:p></o:p></span></pre><pre style='text-align:center'><span lang=SV>=============================================================================================<o:p></o:p></span></pre><p class=MsoNormal style='margin-bottom:12.0pt;text-autospace:none'><span style='font-size:12.0pt'>This special session addresses all aspects of on-chip communication architecture design and test for multi-core and many-core systems. It presents new ideas in the on-chip communication field such as theory and modeling, scalable and fault tolerant design approaches and frameworks, tools and applications, analysis and comparison, design techniques and emerging implementations.<o:p></o:p></span></p><p class=MsoNormal style='margin-bottom:12.0pt;text-autospace:none'><span style='font-size:12.0pt'>All accepted papers will be included in the proceedings of IEEE MCSoC-15 symposium, which are available worldwide through the <b>IEEE Xplore Digital Library</b>. An extended version of the best papers of the OCA-MC be invited to submit extended article versions to one of the <b>ISI-indexed high-quality journals</b>.<o:p></o:p></span></p><p class=MsoNormal style='text-autospace:none'><span style='font-size:12.0pt'><o:p> </o:p></span></p><p class=MsoNormal style='text-autospace:none'><span style='font-size:12.0pt'>Authors are invited to submit high quality papers representing original work from both the academia and industry in (but not limited to) the following topics:<o:p></o:p></span></p><p class=MsoNormal style='text-autospace:none'><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Design space exploration and tradeoff analysis<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Novel bus and networks-on-chip architectures, including cluster interconnects<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Switching, buffering, topology, routing, and mapping algorithms<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Flow control and congestion management<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Virtualization, QoS, guaranteed throughput and on-chip real time communication<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Router microarchitecture<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Power and energy issues<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Dependable architectures<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>On-chip communication architectures for the dark silicon era<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Fault tolerance and reliability issues<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Dynamic on-chip network reconfiguration<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Modeling and evaluation<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>On-chip communication support for memory and cache access<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>3D on-chip architectures, emerging technologies and new design paradigms<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Timing, synchronous/asynchronous on-chip communication<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Interconnection physical link design<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Testing and verification of on-chip interconnection devices<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>System prototyping<o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:black'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt;color:black'>Industrial practices and case studies <o:p></o:p></span></p><p class=MsoListParagraph style='margin-left:72.0pt;text-indent:-18.0pt;mso-list:l0 level1 lfo2;text-autospace:none'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol;color:white'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><b><span style='font-size:12.0pt;color:white'>IMPORTANT DATES<o:p></o:p></span></b></p><p class=MsoNormal style='text-autospace:none'><b><span style='font-size:12.0pt'>Important Dates<o:p></o:p></span></b></p><p class=MsoNormal style='text-autospace:none'><b><span style='font-size:12.0pt;color:red'><o:p> </o:p></span></b></p><p class=MsoNormal style='text-autospace:none'><b><span style='font-size:12.0pt;color:red'>Deadline for paper submission: 31st March 2015<o:p></o:p></span></b></p><p class=MsoNormal style='text-autospace:none'><span style='font-size:12.0pt;color:black'>Acceptance notification: 22ed June 2015<o:p></o:p></span></p><p class=MsoNormal style='text-autospace:none'><span style='font-size:12.0pt;color:black'>Camera ready paper due: 30th June 2015<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:12.0pt;color:black'><o:p> </o:p></span></p><p class=MsoNormal><b><span style='font-size:12.0pt'>Special session chairs:<span style='color:#1F497D'><o:p></o:p></span></span></b></p><p class=MsoNormal><span style='color:#1F497D'><o:p> </o:p></span></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l1 level1 lfo4'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt'>Hannu Tenhunen (Royal Institute of Technology (KTH), Sweden)<o:p></o:p></span></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l1 level1 lfo4'><![if !supportLists]><span style='font-size:12.0pt;font-family:Symbol'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt'>Pasi Liljeberg (University of Turku, Finland)<o:p></o:p></span></p><p class=MsoListParagraph style='text-indent:-18.0pt;mso-list:l1 level1 lfo4'><![if !supportLists]><span style='font-family:Symbol'><span style='mso-list:Ignore'>·<span style='font:7.0pt "Times New Roman"'> </span></span></span><![endif]><span dir=LTR></span><span style='font-size:12.0pt'>Amir-Mohammad Rahmani <span style='color:#1F497D'> </span>(University of Turku, Finland) </span><o:p></o:p></p></div></body></html>