[ecoop-info] [dsd2009-l] Call for Participation Digital System Design 2009

[antonio.nunez at iuma.ulpgc.es]

Call for Participation

2009 12th EUROMICRO Conference on Digital System Design
"Architectures, Methods and Tools"
DSD 2009, 27-29 August, Patras, Greece
General and Organizing Chairs: Odysseas Koufopavlou, Paris Kitsos,  
Nicolas Sklavos, Henri Basson
Program Chair: Antonio Nunez
Deputy Program Chair: Pedro P. Carballo

Full program, registration and other details available at:
www.dsdconf.org
http://www.vlsi.ee.upatras.gr/~euromicro/

Keynote-1 Thursday 27th
Chair: Antonio Nunez, IUMA/University of Las Palmas GC, Spain
TransMutations: Towards a human-quality optimizing compiler
Alex Nicolau, Computer Science Department, University of California, Irvine

Keynote-2 Friday 28th
Chair: Lech Jozwiak, Eindhoven University of Technology, The Netherlands
Enabling the next major step in migrating hardware designs to software
Jeroen Leijten, Co-Founder and Chief Technology Officer, Silicon Hive,  
Eindhoven

Keynote-3 Saturday 29th
Chair: José Matos, University of Porto, Portugal
A revolution in the semiconductor Industry? The shift of innovation to  
the edges
Juan-Antonio Carballo, IBM Microelectronics Services, San Francisco

Sessions
Thursday 27th

MPSoC-1: Systems-on-a-Chip and MultiProcessor SoCs (1)
Chair: Stylianos Mamagkakis, IMEC, Belgium
1. A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC
Hajer Chtioui, Rabie Ben Atitallah, Smail Niar, Jean-Luc Dekeyser, and  
Mohamed Abid
2. An Efficient Hardware Architecture for Packet Re-sequencing in Network
Processors MPSoCs
Shadi Traboulsi, Michael Meitinger, Rainer Ohlendorf, and Andreas Herkersdorf
3. An Effective Replacement Strategy of Cache Memory for an SMT Processor
Yoshiyasu Ogasawara and Hironori Nakajo
4. An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
Pierfrancesco Foglia, Francesco Panicucci, Cosimo Antonio Prete, and  
Marco Solinas

SS-1: System Synthesis (1)
José Matos, University of Porto, Portugal
1. A Priority-Based Budget Scheduler with Conservative Dataflow Model
Marcel Steine, Marco Bekooij, and Maarten Wiggers
2. Improving the Performance of the Divide-Add Fused Operation Using
Variable Latency Quotient Generation
Alexandru Amaricai and Oana Boncalo
3. Distributed Collaborative Design of a Mixed-Signal IP Component
Adam Pawlak, Piotr Penkala, Pawe? Fras, Wojciech Sakowski, Günter Grau,
Szymon Grzybek, and Alexander Stanitzki

CD-1: Circuit Design (1)
Chair: Nicolas Sklavos, TEI of Patras, Greece
1. A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM
Signaling
Mohammad Fattah, Soodeh Aghli Moghaddam, and Siamak Mohammadi
2. Improving Latency of Quantum Circuits by Gate Exchanging
Naser Mohammadzadeh, Morteza Saheb Zamani, and Mehdi Sedighi
3. Run-Time Reconfigurable Array Using Magnetic RAM
Victor Silva, Luis B. Oliveira, Jorge R. Fernandes, Mário P. Véstias,  
and Horácio C. Neto

FTD-1: Fault Tolerance in Digital System Design (1)
Chair: Peter Tummeltshammer, Vienna University of Technology, Austria
1. Robustness Check for Multiple Faults Using Formal Techniques
Stefan Frehse, Görschwin Fey, André Süflow, and Rolf Drechsler
2. Instruction Precomputation for Fault Detection
Demid Borodin, B.H.H. (Ben) Juurlink, and Stefanos Kaxiras
3. Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four
State Logic
Werner Friesenbichler and Andreas Steininger
4. High Availability Fault Tolerant Architectures Implemented into FPGAs
Martin Straka and Zdenek Kotasek

MPSoC-2: Systems-on-a-Chip and MultiProcessor SoCs (2)
Chair: Smail Niar, INRIA/University of Valenciennes, France
1. Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip
Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, and Vincenzo Catania
2. Exploration of Slot Allocation for On-Chip TDM Virtual Circuits
Li Tong, Zhonghai Lu, and Hua Zhang
3. Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms
Amit Kumar Singh, Wu Jigang, Alok Prakash, and Thambipillai Srikanthan
4. Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip
Networks
Alexander Wei Yin, Liang Guang, Ethiopia Nigussie, Pasi Liljeberg,  
Jouni Isoaho, and Hannu Tenhunen

SS-2: System Synthesis (2)
Chair: Tsutomu Sasao, Kyushu Institute of Technology, Japan
1. Power Management Aware Low Leakage Behavioural Synthesis
Sven Rosinger, Kiril Schröder, and Wolfgang Nebel
2. Variation-tolerant Design Using Residue Number System
Ioannis Kouretas and Vassilis Paliouras
3. Optimized Reconfigurable RTL Components for Performance Improvements
During High-Level Synthesis
George Economakos and Sotiris Xydis
4. Combined SD-RNS Constant Multiplication
E. Vassalos and D. Bakalis

CD-2: Circuit Design (2)
Chair: Paris Kitsos, Hellenic Open University, Greece
1. Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures
Ayse K. Coskun, Andrew B. Kahng, and Tajana Simunic Rosing
2. Calibration Method for a CMOS 0.06mm^2 150MS/s 8-bit ADC
Nikos Petrellis, Michael Birbas, John Kikidis, and Alexios Birbas
3. Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver  
Circuit for Large Capacitive Load and Low-energy Applications
José Carlos García-Montesdeoca, Juan A. Montiel-Nelson, Saeid  
Nooshabadi, J. Sosa, and Héctor Navarro

PI-1: Poster Introduction / Poster Session (1)
Chair: Pedro P. Carballo, IUMA/University of Las Palmas GC, Spain
1. An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs
Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, and Hannu Tenhunen
2. Model-Driven Design of Embedded Multimedia Applications on SoCs
Adolf Abdallah, Abdoulaye Gamatié, and Jean-Luc Dekeyser
3. GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform
Grids
Alexandre Solon Nery, Nadia Nedjah, and Felipe Maia Galvão França
4. Using Integer Linear Programming in Test-bench Generation for Evaluating
Communication Processors
Eric Senn, David Monnereau, André Rossi, and Nathalie Julien
5. Reliability Estimation Process
T. Koal, Daniel Scheit, and Heinrich Theodor Vierhaus
6. Time-Varying Network Fault Model for the Design of Dependable Networked
Embedded Systems
Franco Fummi, Davide Quaglia, and Francesco Stefanni
7. Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems
Raimund Ubar, Sergei Kostin, and Jaan Raik
8. High Performance Image Processing on a Massively Parallel Processor  
Array Roberto R. Osorio, César Díaz-Resco, and Javier D. Bruguera

MPSoC-3: Systems-on-a-Chip and MultiProcessor SoCs (3)
Chair: Stylianos Mamagkakis, IMEC, Belgium
1. Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail
Test Environment
Zhiyuan He, Zebo Peng, and Petru Eles
2. Low Power Encoding in NoCs Based on Coupling Transition Avoidance
Meysam Taassori and Shaahin Hessabi
3. Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources
Andreas Lankes, Thomas Wild, and Andreas Herkersdorf
4. Storage Architecture for an On-chip Multi-core Processor
Mengxiao Liu, Weixing Ji, Jiaxin Li, and Xing Pu

SAC: Synthesis of Arithmetic Circuits
Chair: Tsutomu Sasao, Kyushu Institute of Technology, Japan
1. Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs
Rui Duarte, Horácio Neto, and Mário Véstias
2. A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC
Feng Liu, Fariborz Fereydouni Forouzandeh, Otmane Ait Mohamed, Gang Chen,
Xiaoyu Song, and Qingping Tan
3. Streaming Reduction Circuit
Marco Gerards, Jan Kuper, André Kokkeler, and Bert Molenkamp
4. Variable Latency Rounding for Golschmidt Algorithm with Parallel
Remainder Estimation
Daniel Piso Fernandez and Javier Diaz Bruguera

CD-3: Circuit Design (3)
Chair: George Economakos, National Technical University of Athens, Greece
1. Pulse Generation for On-chip Data Transmission
Simon J. Hollis
2. High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V
Input and 1V Output
José Carlos García-Montesdeoca, Juan A. Montiel-Nelson, and Saeid Nooshabadi
3. Performance-Effective Compaction of Standard-Cell Libraries for Digital
Design
Andrea Ricci, Ilaria De Munari, and Paolo Ciampolini

FTD-2: Fault Tolerance in Digital System Design (2)
Chair: Zdenek Kotasek, Brno University of Technology, Czech Republic
1. On the Risk of Fault Coupling over the Chip Substrate
Peter Tummeltshammer and Andreas Steininger
2. Heterogeneous Multiprocessor Synthesis under Performance and Reliability
Constraints
Makoto Sugihara
3. A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded
Systems
Jimmy Tarrillo, Letícia Maria Bolzani Pöhls, and Fabian Vargas
4. Reliable Railway Station System Based on Regular Structure  
Implemented in FPGA
Jaroslav Borecký, Pavel Kubalík, and Hana Kubátová
5. Dependable Controller Design Using Polymorphic Counters
Richard Ruzicka

Friday 28th

MPSoC-4: Systems-on-a-Chip and MultiProcessor SoCs (4)
Chair: Smail Niar, INRIA/University of Valenciennes
1. Internet-Router Buffered Crossbars Based on Networks on Chip
Kees Goossens, Lotfi Mhamdi, and Iria Varela Senín
2. Network-on-Chip Architecture Exploration Framework
Timo Schönwald, Jochen Zimmermann, Oliver Bringmann, and Wolfgang Rosenstiel
3. Meta-model Assisted Optimization for Design Space Exploration of  
Multi-Processor Systems-on-Chip
Giovanni Mariani, Gianluca Palermo, Cristina Silvano, and Vittorio Zaccaria
4. Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A
Network-on-Chip Case Study
Alexandre Guerre, Nicolas Ventroux, Raphaël David, and Alain Mérigot

SLE: System-Level Energy Optimization of HW/SW Embedded Systems
Chair: Davide Quaglia, University of Verona, Italy
1. A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for  
Fine Grain SoC Tuning (Invited paper)
Ahmed Mohamed AbdelHamid, Ankur Anchlia, Stylianos Mamagkakis,
Miguel Corbalan Miranda, Bart Dierickx, and Maarten Kuijk
2. Conservative Dynamic Energy Management for Real-Time Dataflow
Applications Mapped on Multiple Processors
Anca Molnos and Kees Goossens
3. Compilation Technique for Loop Overhead Minimization
Nikolaos Kroupis, Praveen Raghavan, Murali Jayapala, Francky Catthoor,  
and Dimitrios Soudris
4. Pipelining-Based High Throughput Low Energy Mapping on Network-on-Chip
Ming-Yan Yu, Ming Li, Jun-Jie Song, Fang-Fa Fu, and Yu-Xin Bai

FDR-1: Flexible Digital Radio (1)
Chair: Dominique Noguet, Minatec CEA-LETI, France
1. Open Platform for Prototyping of Advanced Software Defined Radio  
and Cognitive Radio Techniques
Dominique Nussbaum, Karim Kalfallah, Christophe Moy, Amor Nafkha,  
Pierre Lerary,
Julien Delorme, Jacques Palicot, Jérôme Martin, Fabien Clermidy,  
Bertrand Mercier, and Renaud Pacalet
2. Architecture and DSP Implementation of a DVB-S2 Baseband  
Demodulator Panayiotis Savvopoulos, Nikolaos Papandreou, and Theodore  
Antonakopoulos
3. An Open and Reconfigurable Platform for 4G Telecommunication:  
Concepts and Application
Fabien Clermidy, Romain Lemaire, Xavier Popon, Dimitri Kténas, and  
Yvain Thonnart

FTDT: Fault Tolerance, Dependability and Testing
Chair: Hana Kubátová, Czech Technical University in Prague, Czech Republic
1. Deductive Fault Simulation for Asynchronous Sequential Circuits
Roland Dobai and Elena Gramatová
2. ARROW - A Generic Hardware Fault Injection Tool for NoCs
Michael Birner and Thomas Handl
3. A Fault Tolerant NoC Architecture for Reliability Improvement and Latency
Reduction
Amir Ehsani Zonouz, Mehrdad Seyrafi, Arghavan Asad, Mohsen Soryani,
Mahmoud Fathy, and Reza Berangi
4. Reliability Analysis of Qubit Data Movement for Distributed Quantum
Computation
Oana Boncalo and Alexandru Amaricai
5. High Reliable Remote Terminal Unit for Space Applications
David Guzmán, Manuel Prieto, Daniel García, Victor Ruíz, Javier Almena,
Sebastián Sánchez, and Daniel Meziat

PSS-1: Processor and System Synthesis (1)
Chair: Jacques Tiberghien, Vrije Universiteit Brussel, Belgium
1. SIMD Architectural Enhancements to Improve the Performance of the  
2D Discrete Wavelet Transform
Asadollah Shahbahrami and Ben Juurlink
2. Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch
Mechanism
Zheng Shen, Hu He, and Yihe Sun
3. Iterative Algorithm for Compound Instruction Selection with Register
Coalescing
Minwook Ahn, Jonghee M. Youn, Youngkyu Choi, Doosan Cho, and Yunheung Paek
4. CPLD-oriented Synthesis of Finite State Machines
Robert Czerwinski and Dariusz Kania

SS-3: System Synthesis (3)
Chair: Adam Pawlak, Silesian University of Technology, Poland
1. Architecture-Driven Synthesis of Reconfigurable Cells
Christophe Wolinski, Krzysztof Kuchcinski, Erwan Raffin, and Francois Charot
2. An on Chip Network inside a FPGA for Run-Time Reconfigurable Low
Latency Grid Communication
Jochen Strunk, Toni Volkmer, Wolfgang Rehm, and Heiko Schick
3. Composable Resource Sharing Based on Latency-Rate Servers
Benny Akesson, Andreas Hansson, and Kees Goossens

FDR-2: Flexible Digital Radio (2)
Chair: Dominique Noguet, Minatec CEA-LETI, France
1. A MPSoC Prototyping Platform for Flexible Radio Applications
Damien Hedde, Pierre-Henri Horrein, Frédéric Pétrot, Robin Rolland,  
and Franck Rousseau
2. Abstract Description of System Application and Hardware  
Architecture for Hardware/Software Code Generation
Amin El Mrabti, Hamed Sheibanyrad, Frédéric Rousseau, Frédéric Petrot,
Romain Lemaire, and Jérôme Martin
3. Reconfiguration Level Analysis of FFT / FIR Units in Wireless
Telecommunication Systems
Maroun Ojail, Raphaël David, Stéphane Chevobbe, and Didier Demigny
4. Flexible Architectures for LDPC Decoders Based on Network on Chip
Paradigm
Fabrizio Vacca, Guido Masera, Hazem Moussa, Amer Baghdadi, and Michel Jezequel

PI-2: Poster Introduction / Poster Session (2)
Chair: Sebastián López, IUMA/University of Las Palmas GC, Spain
1. High Performance CMOS 2-input NAND Based on Low-race Split-level
Charge-recycling Pass-transistor Logic
José Carlos García-Montesdeoca, Juan A. Montiel-Nelson, and Saeid Nooshabadi
2. Power Aware Fulfilment of Latency Requirements by Exploiting
Heterogeneity in Wireless Sensor and Actuator Networks
Joris Borms, Kris Steenhaut, Bart Lemmens, and Ann Nowé
3. The Case for a Balanced Decomposition Process
Jan Schmidt and Petr Fi?er
4. Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost
Minimization
Petr Miku?ek and Václav Dvorák
5. Design, Simulation and Performance Evaluation of a NAND Based
Single-electron 2-4 Decoder
Thomas Tsiolakis, Nikos Konofaos, and George Alexiou
6. Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric
Multiprocessor Architecture
Marius Gligor, Nicolas Fournel, and Frédéric Pétrot
7. Survey of Test Data Compression Technique Emphasizing Code Based
Schemes
Usha Sandeep Mehta, K.S. Dasgupta, and N.M. Devashrayee
8. A Concept for Logic Self Repair
Tobias Koal, Heinrich Theodor Vierhaus, and Daniel Scheit

PSS-2: Processor and System Synthesis (2)
Chair: Jacques Tiberghien, Vrije Universiteit Brussel, Belgium
1. A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for  
an Asynchronous Processor
Luis A. Tarazona, Doug A. Edwards, and Luis A. Plana
2. An Efficient Low-Complexity Alternative to the ROB for Out-of-Order
Retirement of Instructions
Salvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro López, and Jose Duato
3. An Effective Methodology to Multi-objective Design of Application
Domain-specific Embedded Architectures
Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide  
Patti, and Gianmarco De Francisci Morales
4. Energy and Performance Model of a SPARC Leon3 Processor
Sandro Penolazzi, Luca Bolognino, and Ahmed Hemani

RC-1: Programmable/Re-Configurable Architectures (1)
Chair: George Economakos, National Technical University of Athens, Greece
1. Acceleration of MELP Algorithm Using DSP Coprocessor with Extended
Registers
Lu Gao, Li Guo, and Canxing Lu
2. FPGA Accelerator for RNA Secondary Structure Prediction
Arturo Díaz-Pérez and Mario A. García-Martínez
3. An FPGA-Based Embedded System for Fingerprint Matching Using
Phase-Only Correlation Algorithm
G. Danese, M. Giachero, F. Leporati, G. Matrone, and N. Nazzicari
4. xMAML: A Modeling Language for Dynamically Reconfigurable
Architectures
Julien Lallet, Sébastien Pillement, and Olivier Sentieys

APP-1: Applications of (Embedded) Digital Systems (1)
Chair: Henri Basson, University of Littoral, France
1. A High Performance Hardware Architecture for One Bit Transform Based
Motion Estimation
Abdulkadir Akin, Yigit Dogan, and Ilker Hamzaoglu
2. Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding
Supporting HSPA Evolution
Rizwan Asghar, Di Wu, Johan Eilert, and Dake Liu
3. GPU Accelerated Solver of Time-Dependent Air Pollutant Transport
Equations
Vaclav Simek, Radim Dvorak, Frantisek Zboril, and Vladimir Drabek
4. A Reconfigurable Frame Interpolation Hardware Architecture for High
Definition Video
Ozgur Tasdizen and Ilker Hamzaoglu

DTD: Dependability and Testing of Digital Systems
Chair: Hana Kubátová, Czech Technical University in Prague, Czech Republic
1. Transactions Sequence Tracking by means of Dynamic Binary  
Instrumentation of TLM Models
Antonio da Silva and Sebastián Sánchez
2. Design of a Highly Dependable Beamforming Chip
Xiao Zhang and Hans G. Kerkhoff
3. One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k)
Extended Euclidean Algorithm
Apostolos P. Fournaris and Odysseas Koufopavlou
4. Signal Integrity and Power Integrity Methodology for Robust  
Analysis of On-the-Board System for High Speed Serial Links
Raj Kumar Nagpal, Rakesh Malik, and Jai Narayan Tripathi

Saturday 29th

LS: Logic Synthesis
Chair: Jan Schmidt, Czech Technical University in Prague, Czech Republic
1. Synthesizing Reversible Circuits for Irreversible Functions
D. Michael Miller, Robert Wille, and Gerhard W. Dueck
2. A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms
Petr Fi?er and David Toman
3. Representation of Incompletely Specified Index Generation Functions Using
Minimal Number of Compound Variables
Tsutomu Sasao, Takaaki Nakamura, and Munehiro Matsuura
4. Logic Minimization and Testability of 2SPP-P-Circuits
Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, and Tiziano Villa

RC-2: Programmable/Re-Configurable Architectures (2)
Francesco Leporati, University of Pavia, Italy
1. FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, LANE,
Shabal and Spectral Hash
Brian Baldwin, Andrew Byrne, Mark Hamilton, Neil Hanley, Robert P. McEvoy,
Weibo Pan, and William P. Marnane
2. Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p
System and FPGA Implementation Using an ESL Methodology
George Kiokes, George Economakos, Angelos Amditis, and Nikolaos Uzunoglu
3. Stereo Vision Algorithm Implementation in FPGA Using Census  
Transform for Effective Resource Optimization
Mario Alberto Ibarra-Manzano, Dora-Luz Almanza-Ojeda, Michel Devy,
Jean-Louis Boizard, and Jean-Yves Fourniols

APP-2: Applications of (Embedded) Digital Systems (2)
Chair: Henri Basson, University of Litoral, France
1. The Parallel Sieve Method for a Virus Scanning Engine
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, and Yoshifumi Kawamura
2. Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery
Modular Inverse Algorithm
Hamid Reza Ahmadi and Ali Afzali-Kusha
3. Methodology for Fast Pattern Matching by Deterministic Finite  
Automaton with Perfect Hashing
Jan Kastil, Jan Korenek, and Ondrej Lengal
4. An FPGA-Based Embedded System for a Sailing Robot
José Carlos Alves and Nuno Alexandre Cruz

WSN: Wireless Sensor Networks
Chair: William Fornaciari, Politecnico di Milano, Italy
1. Ad-hoc WSN in Biological Research
Perfecto Mariño, Fernando Pérez Fontán, Miguel Ángel Domínguez, and  
Santiago Otero
2. Low Power Free Space Optical Communication in Wireless Sensor Networks
James Mathews, Matthew Barnes, and D.K. Arvind
3. A Framework for Compile-time and Run-time Management of Non-functional
Aspects in WSN Nodes
Carlo Brandolese and William Fornaciari
4. Remote Monitoring of Thermal Performance of Salinity Gradient Solar Ponds
Milan Nenad Simic, Randeep Singh, Louis Doukas, and Aliakbar Akbarzadeh