[ecoop-info] [CFP] IA^3 2014 - SC14 Workshop on Irregular Applications: Architectures & Algorithms

Tumeo, Antonino Antonino.Tumeo at pnnl.gov
Fri Aug 1 21:01:05 CEST 2014

[Please accept our apologies if you receive multiple copies of this Call for Papers (CFP).]

IA^3 2014 - SC14 Workshop on Irregular Applications: Architectures & Algorithms
New Orleans, LA
November 16, 2014

Held in conjunction with SC14 (http://sc14.supercomputing.org)
Held in cooperation with SIGHPC (http://www.sighpc.org)


Irregular applications span a broad range of applications with unpredictable memory access patterns, control structures, and/or network transfers. They typically use pointer-based data structures such as graphs and trees, often present fine-grained synchronization and communication, and generally operate on very large data sets. They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to tolerate access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields, such as social network analysis, bioinformatics, semantic graph databases, bioinformatics, Computer Aided Design (CAD) and computer security. Many of these application areas also process massive sets of unstructured data, which keep growing exponentially. Addressing the issues of irregular applications on current and future architectures will become critical to solve the scientific challenges of the next few years.

This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms.  Topics of interest, of both theoretical and practical significance, include but are not limited to:

* Micro- and System-architectures
* Network and memory architectures
* Heterogeneous, custom and emerging architectures (GPUs, FPGAs, multi- and many-cores)
* Modeling, simulation and evaluation of architectures
* Innovative algorithmic techniques
* Parallelization techniques and data structures
* Approaches for managing massive unstructured datasets
* Languages and programming models
* Library and runtime support
* Compiler and analysis techniques
* Graph databases

Besides regular papers, papers describing work-in-progress or incomplete but sound, innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers.


Submission site: https://www.easychair.org/conferences/?conf=ia32014

All submissions should be in double-column, single-spaced letter format, using 9-point size fonts, with at least one-inch margins on each side. 

The proceedings of the workshop will be published in cooperation with ACM SIGHPC, so authors can use the ACM official templates, available at http://www.acm.org/sigs/publications/proceedings-templates, to simplify the editing process.

Submitted manuscripts may not exceed eight pages in length for regular papers and four pages for position papers including figures, tables and references. 

For any question, please contact the organizers. 


Abstract submission:  25 August 2014
Full or position paper submission: 1 September 2014
Notification of acceptance:  3 October 2014
Camera-ready papers: 10 October 2014
Workshop: 16 November 2014


Antonino Tumeo, Pacific Northwest National Laboratory, antonino.tumeo at pnnl.gov
John Feo, Pacific Northwest National Laboratory, john.feo at pnnl.gov
Oreste Villa, NVIDIA Research, ovilla at nvidia.com


Keren Bergman, Columbia University, USA
Jay Brockman, University of Notre Dame, USA
David Brooks, Harvard University, USA
Bryan Catanzaro, NVIDIA, USA
Daniel Chavarria, Pacific Northwest National Laboratory, USA
Srini Devadas, Massachusetts Institute of Technology, USA
Georgi Gaydadjiev, Chalmers University, SWE
Maya Gokhale, Lawrence Livermore National Laboratory, USA
Martha Kim, Columbia University, USA
John Leidel, Texas Tech University, USA
Kamesh Madduri, The Pennsylvania State University, USA	
Alessandro Morari, Pacific Northwest National Laboratory, USA
Timothy Mattson, Intel, USA
Richard Murphy, Micron Technology, Inc., USA
Walid Najjar, University of California Riverside, USA
Kunle Olukotun, Stanford University, USA
Gianluca Palermo, Politecnico di Milano, ITA
Fabrizio Petrini, IBM TJ Watson, USA
Keshav Pingali, University of Texas, Austin, USA
Vivek Sarkar, Rice University, USA
Erik Saule, University of North Carolina at Charlotte, USA
John Shalf, Lawrence Berkeley National Laboratory, USA
Simone Secchi, ARM, UK
Michela Taufer, University of Delaware, USA
Pedro Trancoso, University of Cyprus, CYP
Mateo Valero, Barcelona Supercomputing Center, SPA

Best Regards,
Antonino Tumeo
Research Scientist
High Performance Computing
Pacific Northwest National Laboratory
antonino.tumeo at pnnl.gov

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