[ecoop-info] R&D position in Formal Verification, Advanced Research Center, Atrenta France

[Roberto Bruttomesso]

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Job Description:
================

The research activity will aim at investigating and developing novel
techniques,
methodologies and support tools for the verification of circuit designs in
particular
the use of Satisfiability Modulo Theories (SMT), however researcher with
background
on other verification techniques are also encouraged to apply.


Candidate Profile:
==================

World class researcher in EE/CS/Math (particularly formal theory), familiar
with
predicate logic, temporal logic (e.g., CTL, LTL, PSL, SVA), model checking,
familiar
with complexity of algorithms, very strong in algorithm development --
including
design and implementation of large programs, very  strong in mathematical
considerations in the development of CAD tools/EDA and familiarity with
design
practice.

Intimate knowledge of one solvers such as  BDD, SAT, ATPG, SMT and symbolic
simulation algorithms.

Intimate knowledge of Object-oriented programming language C++.

Capability of working with prospective customers. Experience in a
Semiconductor
company is helpful but not absolutely essential.


Job Requirements:
=================

BS in EE/CS/Math. with 9+ years of relevant experience, MS with 7+ years of
relevant
experience, or related Ph.D.


It is essential that the individual has strong desires to learn and explore
new
technologies and are able to demonstrate good analysis and problem solving
skills.
Prior knowledge and experience of CAD tool/EDA development are a big plus.


Contact:
========

FAHIM RAHIM,PhD
SR. DIRECTOR OF ENGINEERING

Atrenta Inc.
7 parvis Louis Néel
38000 Grenoble, France

 email fahim at atrenta.com
direct             +33.4.38.12.05.91       ext
431<%2B33.4.38.12.05.91%20ext%20431>

   fax +33.4.76.84.65.51
  cell +33.6.6.32.57.64.19
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