[ecoop-info] CfP: SPECIAL SESSION on On-chip Communication Architectures for Multi-Core and Many-Core Systems in IEEE MCSoC Symposium

[Amir Rahmani]

[Apologies if you receive multiple copies of this CFP.] 

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CALL FOR PAPERS
On-chip Communication Architectures for Multi-Core and Many-Core Systems
(OCA-MC)
Special session in IEEE 9th International Symposium on Embedded
Multicore/Many-core Systems-on-Chip (MCSoC-15)
http://mcsoc-forum.org/2015/?page_id=14
23-25 September 2015, Turin, Italy
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This special session addresses all aspects of on-chip communication
architecture design and test for multi-core and many-core systems. It
presents new ideas in the on-chip communication field such as theory and
modeling, scalable and fault tolerant design approaches and frameworks,
tools and applications, analysis and comparison, design techniques and
emerging implementations.

All accepted papers will be included in the proceedings of IEEE MCSoC-15
symposium, which are available worldwide through the IEEE Xplore Digital
Library. An extended version of the best papers of the OCA-MC be invited to
submit extended article versions to one of the ISI-indexed high-quality
journals.

 

Authors are invited to submit high quality papers representing original work
from both the academia and industry in (but not limited to) the following
topics:

 

.         Design space exploration and tradeoff analysis

.         Novel bus and networks-on-chip architectures, including cluster
interconnects

.         Switching, buffering, topology, routing, and mapping algorithms

.         Flow control and congestion management

.         Virtualization, QoS, guaranteed throughput and on-chip real time
communication

.         Router microarchitecture

.         Power and energy issues

.         Dependable architectures

.         On-chip communication architectures for the dark silicon era

.         Fault tolerance and reliability issues

.         Dynamic on-chip network reconfiguration

.         Modeling and evaluation

.         On-chip communication support for memory and cache access

.         3D on-chip architectures, emerging technologies and new design
paradigms

.         Timing, synchronous/asynchronous on-chip communication

.         Interconnection physical link design

.         Testing and verification of on-chip interconnection devices

.         System prototyping

.         Industrial practices and case studies 

.         IMPORTANT DATES

Important Dates

 

Deadline for paper submission: 31st March 2015

Acceptance notification: 22ed June 2015

Camera ready paper due: 30th June 2015

 

Special session chairs:

 

.         Hannu Tenhunen (Royal Institute of Technology (KTH), Sweden)

.         Pasi Liljeberg (University of Turku, Finland)

.         Amir-Mohammad Rahmani  (University of Turku, Finland) 

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