[ecoop-info] [dsd2010-l] EUROMICRO DSD 2010 CALL FOR PARTICIPATION

Sebastian Lopez sebastian.lopez at iuma.ulpgc.es
Tue Jun 15 10:09:18 CEST 2010


2010 13th EUROMICRO Conference on Digital System Design
"Architectures, Methods and Tools"
DSD 2010, 1-3 September, Lille, France
General Chairs: Henri Basson and Smail Niar
Program Chair: Sebastian Lopez

Full program, registration and other details available at:


Keynote 1 - Wednesday 1st September
Cyper-physical MPSoC System:  Adaptive Multi-Core Architectures in the  
Nano Era
Jürgen Becker
Karlsruhe Institute of Technology, Germany

Keynote 2 - Thursday 2nd September
Digital System Design for Remotely Sensed Hyperspectral Image Processing
Antonio J. Plaza
University of Extremadura, Spain

Keynote 3 - Friday 3rd September
Future Directions for Digital Systems Design - A Programmable Perspective
Patrick Lysaght
Xilinx Research Labs, San Jose, CA



SCS-1: System and Circuit Synthesis (1)
Optimization of Area and Delay at Gate-Level in Multiple Constant  
Aksoy, Levent (1); Costa, Eduardo (2); Flores, Paulo (1); Monteiro, José (1)
1: INESC-ID, Lisbon, Portugal; 2: UCPEL, Pelotas-RS, Brazil
Visualization of Multi-Objective Design Space Exploration for Embedded Systems
Taghavi Razavi Zadeh, Toktam; D. Pimentel, Andy
University of Amsterdam, Netherlands, The
Design of Trace-Based Split Array Caches for Embedded Applications
Tokarnia, Alice M.; Tachibana, Marina
School of Electrical and Computer Engineering/University of Campinas, Brazil
Software Programmable Data Allocation in Multi-Bank Memory of SIMD Processors
Wang, Jian; Sohl, Joar; Kraigher, Olof; Liu, Dake
Linkoping University, Sweden

S&N(oC)-1: Systems and Networks on Chip (1)
A Novel Mechanism to Guarantee In-Order Packet Delivery with Adaptive  
Routing Algorithms in Networks on Chip
Palesi, Maurizio (1); Holsmark, Rickard (2); Wang, Xiaohang (3);  
Kumar, Shashi (2); Yang, Mei (3); Jiang, Yingtao (3); Catania,  
Vincenzo (1)       
1: University of Catania, Italy; 2: Jonkoping University, Sweden; 3:  
University of Nevada, USA
Power Distribution in NoCs through a Fuzzy Based Selection Strategy  
for Adaptive Routing
Salehi, Nastaran (1); Khademzadeh, Ahmad (2); Dana, Arash (2)       
1: Islamic Azad University, Science and Research Branch, Tehran, Iran;  
2: Iran Telecommunication Research center, Tehran, Iran       
NoC switch with credit based guaranteed service support qualified for  
GALS systems
Kranich, Tim; Berekovic, Mladen
TU Braunschweig, Germany
A Low Cost Single-Cycle Router Based on Virtual Output Queuing for  
On-Chip Networks       
Nguyen, Son Truong; Oyanagi, Shigeru
Department of Computer Science, Ritsumeikan University, Japan
RC-1: Reconfigurable Computing (1)
Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration
Shehan, Basher; Jahr, Ralf; Uhrig, Sascha; Ungerer, Theo       
University of Augsburg, Germany       
Creation of Partial FPGA Configurations at Run-Time
Silva, Miguel (1); Ferreira, João Canas (1,2)
1: FEUP, Portugal; 2: INESC Porto       
A Modular Peripheral to Support Self-Reconfiguration in SoCs
Otero Marnotes, Andrés; Morales Cas, Ángel; Portilla, Jorge; De la  
Torre, Eduardo; Riesgo, Teresa
Universidad Politécnica de Madrid, Spain
High level validation of an optimization algorithm for the  
implementation of adaptive Wavelet Transforms in FPGAs
Salvador, Rubén (1); Moreno, Félix (1); Riesgo, Teresa (1); Sekanina,  
Lukás (2)
1: Universidad Politécnica de Madrid, Spain; 2: Brno University of  
Technology, Brno, Czech Republic       

SLEO: System Level Energy Optimization of HW/SW Embedded Systems
Composable Dynamic Voltage and Frequency Scaling and Power Management  
for Dataflow Applications
Goossens, Kees (1); She, Dongrui (1); Molnos, Anca (2); Milutinovic,  
Aleksandar (3)       
1: Eindhoven University of Technology, The Netherlands; 2: Delft  
University of Technology, The Netherlands; 3: University of Twente,  
The Netherlands       
A Markov Model for Low-Power High-Fidelity Design-Space Exploration
Cao, Jing; Nymeyer, Albert       
University of New South Wales, Australia       
A Test Bench for Distortion-Energy Optimization of a DSP-Based  
H.264/SVC Decoder
Pescador del Oso, Fernando (1); Juarez Martinez, Eduardo (1); Samper  
Martinez, David (1); Sanz Álvaro, César (1); Raulet, Mickaël (2)       
1: Universidad Politécnica de Madrid, Spain; 2: IETR/Image group Lab,  
Rennes, France

SCS-2: System and Circuit  Synthesis (2)
On Reducing Error Rate of Data Protected Using Systematic Unordered  
Codes in Asymmetric Channels
Piestrak, Stanislaw J.       
QoR Analysis of Automated Clock-Mesh Implementation under OCV Consideration
Bode, Dennis; Berekovic, Mladen       
TU Braunschweig, Germany
A C-to-RTL flow as an energy efficient alternative to embedded  
processors in digital systems
Desai, Madhav Pandurang; Sahasrabuddhe, Sameer D; Ghosh, Kunal P;  
Subramanian, Sreenivas; Arya, Kavi
Indian Institute of Technology Bombay, India
Area and Speed Oriented Implementations of Asynchronous Logic  
Operating Under Strong Constraints
Fiser, Petr (1); Lemberski, Igor (2)       
1: Czech Technical University in Prague, Czech Republic; 2: Baltic  
International Academy, Riga, Latvia

S&N(oC)-2: Systems and Networks on Chip (2)
A Latency-Efficient Router Architecture for CMP Systems
Roca, Antoni; Flich, Jose; Silla, Federico; Duato, Jose       
Technical University of Valencia, Spain
Trading hardware overhead for communication performance in mesh-type  
Cornelius, Claas; Kubisch, Stephan; Gorski, Philipp; Timmermann, Dirk       
University of Rostock, Germany       
Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms
Mubeen, Saad; Kumar, Shashi       
Jönköping University Sweden, Sweden

MSDA-1: Multicore Systems: Design and Applications (1)
Evaluating OpenMP support costs on MPSoCs
Marongiu, Andrea; Burgio, Paolo; Benini, Luca       
University of Bologna, Italy
Re-NUCA: Boosting CMP performance through block replication
Solinas, Marco (1); Foglia, Pierfrancesco (1); Prete, Cosimo Antonio  
(1); Monni, Giovanna (2)       
1: Università di Pisa, Italy; 2: IMT Institute for Advanced Studies       
Filtering Directory Lookups in CMPs
Bosque, Ana (1); Viñals, Víctor (2); Ibáñez, Pablo (2); Llabería, Jose  
M. (1)       
1: UPC, Spain; 2: Universidad de Zaragoza, Spain

FTDSD-1: Fault Tolerance in Digital System Design (1)
Low Latency Recovery from Transient Faults for Pipelined Processor  
Jeitler, Marcus       
Vienna University of Technology, Austria       
RobuCheck: A Robustness Checker for Digital Circuits
Frehse, Stefan; Fey, Goerschwin; Sueflow, Andre; Drechsler, Rolf       
University of Bremen, Germany
Dynamic Control Flow Checking Technique for Reliable Microprocessors       
Sugihara, Makoto       
TUT, Japan
Poster Session P-1
Arithmetic units for RNS moduli $\{2^{n}-3\}$ and $\{2^{n}+3\}$ operations
Matutino, Pedro Miguens (1); Chaves, Ricardo (2); Sousa, Leonel (2)       
1: ISEL / INESC-ID, Portugal; 2: IST / INESC-ID, Portugal
Real-time Testing of True Random Number Generators through Dynamic  
Cret, Octavian Augustin; Hotoleanu, Dan; Suciu, Alin; Vacariu, Lucia       
Tehnical University of Cluj Napoca - Romania, Romania
Instantiating GENESYS Application Architecture Modelling via UML 2.0  
constructs and MARTE Profile
Khan, Subayal Aftab (1); Tiensyrjä, Kari (1); Nurmi, Jari (2)       
1: VTT Technical Research Centre of Finland; 2: Tampere University of  
An Improved Automotive Multiple Target Tracking System Design       
Lange, Tobias (1); Harb, Naim (2); Ben-Atitallah, Rabie (2); Liu,  
Haisheng (2); Niar, Smail (2)       
1: Technical University of Braunschweig, Germany;
2: University Of Lille North of France (ULNF), Valenciennes, France
Medical Diagnosis Improvement through Image Quality Enhancement Based  
on Super-Resolution       
G. Villanueva, Lara; M. Callicó, Gustavo; Tobajas, Félix; López,  
Sebastián; De Armas, Valentín; López, José F.; Sarmiento, Roberto       
University of Las Palmas de Gran Canaria, Spain
Generated Cycle-Accurate Profiler for C Language
Prikryl, Zdenek; Masarik, Karel; Hruska, Tomas; Husar, Adam       
Brno University of Technology, Czech Republic
Architecture Level Design Space Exploration of SuperScalar  
Microarchitecture for Network Applications
Salehi, Mostafa E; Dorosti, Hamed; Fakhraie, Sied Mehdi       
University of Tehran, Iran, Islamic Republic of
SVMT-1: System, hardware and embedded-software specification,  
modeling, verification and test (1)
Simulation of High-Performance Memory Allocators
Risco-Martín, José Luis; Colmenar, José Manuel; Atienza, David
Universidad Complutense de Madrid, Spain
Test Data and Power Reductions for Transition Delay Tests for  
Massive-Parallel Scan Structures
Kothe, Rene       
BTU Cottbus, Germany       
Exploration of Network Alternatives for Middleware-centric Embedded  
System Design
Quaglia, Davide; Fummi, Franco; Perbellini, Giovanni; Trenti, Roberto
University of Verona, Italy
FDR: Flexible Digital Radio
Adaptive Beamforming using the Reconfigurable Montium TP
van de Burgwal, Marcel D.; Rovers, Kenneth C.; Blom, Koen C.H.;  
Kokkeler, André B.J.; Smit, Gerard J.M.University of Twente,  
Netherlands, The
A Common Operator for FFT and Viterbi algorithms
Naoues, Malek; Alaus, Laurent; Noguet, Dominique       
CEA, France
ALOE-based flexible LDPC decoder
Gomez Miguelez, Ismael (1); Camatel, Massimo (1); Bracke, Jordi (1);  
Vacca, Fabrizio (2); Marojevic, Vuk (1); Masera, Guido (2); Gelonch,  
1: Universitat Politecnica de Catalunya, Spain; 2: Dipartimento di  
Elettronica, Politecnico di Torino, Italy
Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA
Recio, Adolfo; Athanas, Peter Virginia Tech, United States of America
MSDA-2: Multicore Systems: Design and Applications (2)
Adaptive Cache Memories for SMT Processors
Lopez, Sonia (1); Garnica, Oscar (2); Albonesi, David H. (3); Dropsho,  
Steven (4); Lanchares, Juan (2); Hidalgo, Ignacio (2)       
1: Rochester Institute of Technology, United States of America; 2:  
Universidad Complutense de Madrid, SPAIN; 3: Cornell University, USA.;  
4: Google, Inc Zurich, Switzerland       
Multi-core Technology - Next Evolution Step in Safety Critical Systems  
for Industrial Applications?
Reichenbach, Frank; Wold, Alexander       
ABB, Norway
A Case for Hardware Task Management Support for the StarSS Programming Model
Meenderinck, Cor (1); Juurlink, Ben (2)
1: Delft University of Technology, Netherlands, The; 2: Technische  
Universitat Berlin, Germany
On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on  
Reconfigurable Platforms
Kornaros, George; Motakis, Antonis       
Technological Educational Institute of Crete, Dept. of Applied  
Informatics & Multimedia, Greece
FTDSD-2: Fault Tolerance in Digital System Design (2)
Fault Tolerant Structure for SRAM-based FPGA via Partial Dynamic  
Straka, Martin; Kastil, Jan; Kotasek, Zdenek       
Brno University of Technology, Czech Republic
System Level Hardening by Computing with Matrices
Ferreira, Ronaldo Rodrigues; Moreira, Álvaro Freitas; Carro, Luigi       
Instituto de Informática, Universidade Federal do Rio Grande do Sul,  
Faults Coverage Improvement based on Fault Simulation and Partial Duplication
Borecký, Jaroslav; Kohlík, Martin; Kubátová, Hana; Kubalík, Pavel       
Czech Technical University in Prague, Czech Republic


Poster Session P-2
A Class of Recursive Networks on a Chip for Enhancing Intercluster Parallelism
Takesue, Masaru       
Hosei University, Japan
A programming model and a NoC-based architecture for streaming  
Houzet, Dominique; Huet, Sylvain; Wu, Yun-Jie       
Grenoble INP, France
Scalable Architecture for Wavelength-Switched Optical NoC With  
Multicasting Capability
Koohi, Somayyeh; Shafaei, Alireza; Hessabi, Shaahin       
Sharif University of Technology, Iran, Islamic Republic of
Performance Analysis of 90nm Look Up Table (LUT) for Low Power  
Kumar, Pankaj; Kumar, Deepak; Pattanaik, Manisha
ABV-Indian Institute of Information Technology and Management, Gwalior, India
Area-Efficient Multi-Moduli Squarers for RNS
Bakalis, Dimitris; Vergos, Haridimos T.       
University of Patras, Greece
A Load-Forwarding Mechanism for the Vector Architecture in Multimedia  
Gao, Ye (1); Egawa, Ryusuke (2,3); Takizawa, Hiroyuki (1,3);  
Kobayashi, Hiroaki (2,3)       
1: Graduate School of Information Sciences, Tohoku University; 2:  
Cyberscience Center, Tohoku University; 3: JST CREST
Low Power FPGA Implementations of 256-bit Luffa Hash Function
Kitsos, Paris (1); Sklavos, Nicolas (2); Skodras, Athanassios (3)       
1: Hellenic Open University, Greece; 2: Technological Educational  
Institute of Patras, Greece; 3: Hellenic Open University, Greece
On the Numbers of Variables to Represent Multi-Valued Incompletely  
Specified Functions
Sasao, Tsutomu       
Kyushu Ins. of Tech, Japan
SCS-3: System and Circuit  Synthesis (3)
Unified Digit Serial Systolic Montgomery Multiplication Architecture  
for Special Classes of Polynomials over GF(2^m)
Rahaman, Hafizur; Talapatra, Somsubhra       
Bengal Engineering and Science University, Shibpur, India
An Improved Hardware Implementation of the Grain Stream Cipher
Sharif Mansouri, Shohreh; Dubrova, Elena       
KTH, Sweden
Description-level Optimisation of Synthesisable Asynchronous Circuits
Tarazona Duarte, Luis Antonio; Edwards, Douglas; Bardsley, Andrew  
Plana, Luis       
The University of Manchester, United Kingdom
A parallel for loop memory template for a high level synthesis compiler
Moore, Craig; Stroobandt, Dirk; Meeus, Wim; Devos, Harald       
Ghent University, Belgium

S&N(oC)-3: Systems and Networks on Chip (3)
In-Channel Flow Control Scheme for Network-on-Chip
Nimbalkar, Vrishali Vijay (1); Varghese, Kuruvilla (2)
1: Finolex Academy of Management and Technology, India; 2: Center for  
Electronic Design and Technology, IISc Bangalore, India       
An Efficient Method to Reliable Data Transmission in Network-on-Chips
Patooghy, Ahmad; Tabkhi, Hamed; Miremadi, Seyed Ghassem       
Sharif University of Technology, Iran, Islamic Republic of               
Network-on-Multi-Chip (NoMC) for multi-FPGA multimedia systems
Stepniewska, Marta; Luczak, Adam; Siast, Jakub       
Poznan University of Technology, Poland       
Persistence Management Model for Dynamically Reconfigurable Hardware
Dondo, Julio Daniel; Rincon, Fernando; Barba, Jesus; Moya, Francisco;  
Sanchez, Francisco; Lopez, Juan Carlos
Universidad de Castilla-La Mancha, Spain
WSN: Wireless Sensor Networks
System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes
Pasha, Muhammad Adeel; Derrien, Steven; Sentieys, Olivier       
IRISA-INRIA, University of Rennes1, France
A Traffic Differentiation Add-On to the IEEE 802.15.4 Protocol
Severino, Ricardo; Batsa, Manish; Alves, Mário; Koubaa, Anis
CISTER-ISEP, Portugal       
Evaluating a Transmission Power Self-Optimization Technique for WSN in  
EMI Environments
Lavratti, Felipe (1); Pinto, Alex (2); Bolzani Pöhls, Leticia Maria  
(1); Vargas, Fabian (1); Montez, Carlos (2); Hernandez, Fernando (3);  
Gatti, Edmundo (4); Silva, Carlos (5)
1: Catholic University of Rio Grande do Sul - PUCRS, Brazil; 2:  
Universidade Federal de Santa Catarina - UFSC, Brazil; 3: Unidad  
Reguladora de Servicios de Comunicaciones - URSEC, Uruguay; 4:  
Instituto Nacional de Tecnologia Industrial - INTI, Argentina; 5:  
Pontificia Universidad Católica del Peru, Peru
DTDS-1: Dependability and Testing of Digital Systems (1)
Path-Delay Fault testing in Embedded Content Addressable Memories
Palanichamy, Manikandan; Larsen, Bjørn; Aas, Einar       
The Norwegian University of Science and Technology (NTNU), Norway
Application Dependent FPGA Testing Method Using Compressed  
Deterministic Test Vectors
Rozkovec, Martin; Novák, Ondrej; Jenicek, Jiri
Technical University in Liberec, Czech Republic
On-Chip Scan-Based Test Strategy for a Dependable Many-Core Processor  
Using a NoC as a Test Access Mechanism
Zhang, Xiao (1); Kerkhoff, Hans G. (1); Vermeulen, Bart (2)
1: CTIT, University of Twente, the Netherlands;
2: Distributed Systems Architectures Group, NXP Semiconductors, the  

SCS-4: System and Circuit  Synthesis (4)
Behavioural modelling of DLLs for fast simulation and optimisation of  
jitter and power consumption
Barajas, Enrique; Mateo, Diego; González, José Luis
Universitat Politecnica Catalunya, Spain
A Predictable Multiprocessor Design Flow for Streaming Applications  
with Dynamic Behaviour
Stuijk, Sander (1); Geilen, Marc (1); Basten, Twan (1,2)       
1: Eindhoven University of Technology, The Netherlands; 2: Embedded  
Systems Institute, The Netherlands
A design process for harware/software system co-design and its  
application to designing a reconfigurable FPGA
Moreno, Felix; Lopez, Ignacio; Sanz, Ricardo       
Universidad Politécnica de Madrid (ETSII-UPM), Spain
Optimising Self-timed FPGA circuits
Ferguson, Phillip David (1); Efthymiou, Aristides (2); Arslan, Tughrul  
(2); Hume, Danny (3)
1: Institute Of System Level Integration, United Kingdom; 2:  
University Of Edinburgh, United Kingdom; 3: Thales Optronics Ltd,  
Glasgow, United Kingdom

S&N(oC)-4: Systems and Networks on Chip (4)
A new high-level methodology for programming FPGA-based smart camera
Roudel, Nicolas (1); Berry, François (1); Sérot, Jocelyn (1); Eck, Laurent (2)
1: LASMEA UMR6602, France; 2: CEA, LIST, France
Power consumption modeling for DVFS exploitation
Andrea, Castagnetti; Cécile, Belleudy; Sébastien, Bilavarn; Michel, Auguin
LEAT Université de Nice - CNRS, France       
Automated Power Characterization for Run-Time Power Emulation of SoC Designs
Bachmann, Christian       
Graz University of Technology, Austria
Customizable Composition and Parameterization of Design Transformations       
Todman, Timothy John; Liu, Qiang; Luk, Wayne; Constantinides, George A
Imperial College London, United Kingdom       

ET: Emerging technologies
Architectural Vulnerability Factor Estimation with Backwards Analysis
Hartl, Robert (1); Rohatschek, Andreas J. (1); Stechele, Walter (2);  
Herkersdorf, Andreas (2)
1: Robert Bosch GmbH, Germany; 2: Institute for Integrated Systems,  
Technische Universität München, Germany       
Design of Testable Universal Logic Gate Targeting Minimum  
Wire-Crossings in QCA Logic Circuit
Sen, Bibhash (1); Sengupta, Anik (2); Dalui, Mamta (3); Sikdar, Biplab K (4)
National Institute o Technology Durgapur, India; 2: National Institute  
o Technology Durgapur, India; 3: Bengal Engineering and Science  
University, Shibpur; 4: Bengal Engineering and Science University,  
Evaluation of RTD-CMOS Logic Gates
Nunez, Juan; Avedillo, Maria J.; Quintana, Jose M.
IMSE-CNM-CSIC, Spain       
On CMOS Memory Design In Low Supply Voltage For Integrated Biosensor  
Chen, Tom       
Colorado State University, United States of America
DTDS-2: Dependability and Testing of Digital Systems (2)
A Formal Condition to Stop an Incremental Automatic Functional Diagnosis
Amati, Luca (1); Bolchini, Cristiana (1); Salice, Fabio (1); Franzoso,  
Federico (2)
1: Politecnico di Milano, Italy; 2: Cisco Photonics
The Use of Genetic Algorithm to Derive Correlation Between Test Vector  
and Scan Register Sequences and Reduce Power Consumption 
Kotasek, Zdenek; Skarvada, Jaroslav; Strnadel, Josef
Brno U. of Tech, Czech Republic
Multiple Bit Error Detection and Correction in Memory
Argyrides, Costas (3); Tarrillo, Jimmy (2); Lisboa, Carlos (2);  
Pradhan, Dhiraj (1); Carro, Luigi (2)
1: University of Bristol, United Kingdom; 2: Instituto de Informática,  
PPGC Universidade Federal do Rio Grande do Sul; 3: C. A. evolvIT LTD,  
Limassol, Cyprus


SCS-5: System and Circuit  Synthesis (5)
Design methodology for a high performance robust DVB-S2 decoder implementation
Berthelot, Florent; Charot, François; Wagner, Charles; Wolinski, Christophe
Inria Rennes Irisa, France
Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor
Waqar, Muhammad; Thanh Hoang, Tung; Larson-Edefors, Per
Chalmers University of Technology, Sweden
A Memetic Approach for CMOL Cell Mapping
Zhufei, Chu (1); Yinshui, Xia (1); William, N.N. Hung (2); Xiaoyu,  
Song (3); Lunyao, Wang (1)
1: Ningbo University, China, Peoples Republic of; 2: Synopsys, Inc.,  
USA; 3: Portland State University, USA
Static Average Case Power Estimation Technique for Block Ciphers
Chen, Jiaoyan; Ye, Tingcong; Vasudevan, Dilip; Popovici, Emanuel;  
Schellekens, Michel
University College Cork, Ireland, Republic of
SVMT-2: System, hardware and embedded-software specification,  
modeling, verification and test (2)
An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits
Rutgers, Jochem H. (1); Wolkotte, Pascal T. (2); Hölzenspies, Philip  
K.F. (1); Kuper, Jan (1); Smit, Gerard J.M. (1)
1: University of Twente, Netherlands, The; 2: Alcatel-Lucent, Belgium
Modeling reconfigurable Systems-on-Chips with UML MARTE profile: an  
exploratory analysis
Cherif, Sana; Quadri, Imran; Meftali, Samy; Dekeyser, Jean-Luc       
INRIA Lille-Nord Europe / LIFL / USTL / CNRS, France
C?aSH: Structural Descriptions of Synchronous Hardware using Haskell
Baaij, Christiaan; Kooijman, Matthijs; Kuper, Jan; Boeijink, Arjan;  
Gerards, Marco       
University of Twente, Netherlands, The
Storage-Aware Value Prediction
Baniasadi, Amirali (1); Salehi, Mohammad (2)
1: University of Victoria, Canada; 2: Sharif University of Technology

APP: Applications of (embedded) digital systems
Computation Reduction Techniques for Vector Median Filtering and their  
Hardware Implementation
Tasdizen, Ozgur; Hamzaoglu, Ilker
Sabanci University, Turkey
A Novel VLSI Architecture of Fixed-complexity Sphere Decoder
Wu, Bin; Masera, Guido
Politecnico di Torino, Italy
A Packet Classifier Using a Parallel Branching Program Machine
Nakahara, Hiroki; Sasao, Tsutomu; Matsuura, Munehiro       
Kyushu Institute of Technology, Japan
A Computation and Power Reduction Technique for H.264 Intra Prediction
Adibelli, Yusuf; Parlak, Mustafa; Hamzaoglu, Ilker       
Sabanci University, Turkey
RC-2: Reconfigurable Computing (2)
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance
Sajid, Imtiaz (1); Ziavras, Sotirios (1); Ahmed, M (2)
1: New Jersey Institute of Technology, United States of America; 2:  
Mohammad Ali Jinnah University, Islamabad, Pakistan
An FPGA-based Accelerator for Analog VLSI Artificial Neural Network Emulation
van Liempd, Barend (1); Herrera Peña, Daniel (2); Figueroa Toro, Miguel (2)
1: Eindhoven University of Technology, Netherlands, The; 2: University  
of Concepción, Chile
A Multicore Embedded Processor For Fingerprint Recognition
Leporati, Francesco; Danese, Giovanni; Giachero, Mauro; Nazzicari,  
University of Pavia, Italy
H.264 Color Components Video Decoding Parallelization on Multi-Core  
Baaklini, Elias (1); Sbeity, Hassan (1); Niar, Smail (2)
1: Arab Open University, Beirut, Lebanon; 2: University Of Lille North  
of France (ULNF), Valenciennes, France
Poster Session P-3
New Digital Control Technique for Improving Transient Response in  
DC-DC Converters Batarseh, Majd Ghazi; Shobaki, Ehab; Fang, Xiang; Hu,  
Haibing; Batarseh, Issa
University of Central Florida, United States of America
A Fast Analytical Approach to Multi-Cycle Soft Error Rate Estimation  
of Sequential Circuits
Fazeli, Mahdi; Miremadi, Seyed Ghassem; Asadi, Hossein; Baradaran  
Tahoori, Mehdi
Sharif Uni. of Technology, Iran, Islamic Republic of
A Multicore SDR Architecture for Reconfigurable WiMAX Downlink
Suárez Casal, Pedro; Carro Lagoa, Ángel; García Naya, José Antonio;  
Castedo Ribas, Luis
Universidade da Coruña, Spain
Test Patterns Compression Technique Based on a Dedicated SAT-based  
ATPG                Balcarek, Jiri (1); Fiser, Petr (2); Schmidt, Jan  
1: Czech Technical University in Prague, FEL; 2: Czech Technical  
University in Prague, FIT
Gracefully Degrading Circuit Controllers Based on Polytronics
Ruzicka, Richard       
Brno University of Technology, Czech Republic
LEON3 ViP : a Virtual Platform with Fault Injection capabilities
Da Silva, Antonio (1); Sánchez Prieto, Sebastián (2); Martínez Ortega,  
José Fernán (1); García Hernando, Ana Belen (1); López Santidrian,  
Lourdes (1); Hernández Díaz, Vicente (1)
1: Technical University of Madrid, Spain; 2: University of Alcalá, Spain
Reconfigurable Fault-Tolerant System Sychronization
Balach, Jan; Novak, Ondrej
CTU in Prague, Czech Republic
Structurally Synthesized Multiple Input BDDs for Speeding up  
Logic-Level Simulation of Digital Circuits
Mironov, Dmitri; Ubar, Raimund; Devadze, Sergei; Raik, Jaan; Jutman, Artur
Tallinn Tech. U, Estonia                                       

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